1*6020faf6SRick Chen /* 2*6020faf6SRick Chen * Copyright (C) 2017 Andes Technology Corporation 3*6020faf6SRick Chen * Rick Chen, Andes Technology Corporation <rick@andestech.com> 4*6020faf6SRick Chen * 5*6020faf6SRick Chen * SPDX-License-Identifier: GPL-2.0+ 6*6020faf6SRick Chen */ 7*6020faf6SRick Chen 8*6020faf6SRick Chen #ifndef _ASM_RISCV_CACHE_H 9*6020faf6SRick Chen #define _ASM_RISCV_CACHE_H 10*6020faf6SRick Chen 11*6020faf6SRick Chen /* 12*6020faf6SRick Chen * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. 13*6020faf6SRick Chen * We use that value for aligning DMA buffers unless the board config has 14*6020faf6SRick Chen * specified an alternate cache line size. 15*6020faf6SRick Chen */ 16*6020faf6SRick Chen #ifdef CONFIG_SYS_CACHELINE_SIZE 17*6020faf6SRick Chen #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 18*6020faf6SRick Chen #else 19*6020faf6SRick Chen #define ARCH_DMA_MINALIGN 32 20*6020faf6SRick Chen #endif 21*6020faf6SRick Chen 22*6020faf6SRick Chen #endif /* _ASM_RISCV_CACHE_H */ 23