1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * Freescale I2C Controller 3*a47a12beSStefan Roese * 4*a47a12beSStefan Roese * Copyright 2006 Freescale Semiconductor, Inc. 5*a47a12beSStefan Roese * 6*a47a12beSStefan Roese * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>, 7*a47a12beSStefan Roese * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com), 8*a47a12beSStefan Roese * and Jeff Brown. 9*a47a12beSStefan Roese * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. 10*a47a12beSStefan Roese * 11*a47a12beSStefan Roese * This software may be used and distributed according to the 12*a47a12beSStefan Roese * terms of the GNU Public License, Version 2, incorporated 13*a47a12beSStefan Roese * herein by reference. 14*a47a12beSStefan Roese * 15*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 16*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License 17*a47a12beSStefan Roese * Version 2 as published by the Free Software Foundation. 18*a47a12beSStefan Roese * 19*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 20*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 21*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22*a47a12beSStefan Roese * GNU General Public License for more details. 23*a47a12beSStefan Roese * 24*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 25*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 26*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27*a47a12beSStefan Roese * MA 02111-1307 USA 28*a47a12beSStefan Roese */ 29*a47a12beSStefan Roese 30*a47a12beSStefan Roese #ifndef _ASM_FSL_I2C_H_ 31*a47a12beSStefan Roese #define _ASM_FSL_I2C_H_ 32*a47a12beSStefan Roese 33*a47a12beSStefan Roese #include <asm/types.h> 34*a47a12beSStefan Roese 35*a47a12beSStefan Roese typedef struct fsl_i2c { 36*a47a12beSStefan Roese 37*a47a12beSStefan Roese u8 adr; /* I2C slave address */ 38*a47a12beSStefan Roese u8 res0[3]; 39*a47a12beSStefan Roese #define I2C_ADR 0xFE 40*a47a12beSStefan Roese #define I2C_ADR_SHIFT 1 41*a47a12beSStefan Roese #define I2C_ADR_RES ~(I2C_ADR) 42*a47a12beSStefan Roese 43*a47a12beSStefan Roese u8 fdr; /* I2C frequency divider register */ 44*a47a12beSStefan Roese u8 res1[3]; 45*a47a12beSStefan Roese #define IC2_FDR 0x3F 46*a47a12beSStefan Roese #define IC2_FDR_SHIFT 0 47*a47a12beSStefan Roese #define IC2_FDR_RES ~(IC2_FDR) 48*a47a12beSStefan Roese 49*a47a12beSStefan Roese u8 cr; /* I2C control redister */ 50*a47a12beSStefan Roese u8 res2[3]; 51*a47a12beSStefan Roese #define I2C_CR_MEN 0x80 52*a47a12beSStefan Roese #define I2C_CR_MIEN 0x40 53*a47a12beSStefan Roese #define I2C_CR_MSTA 0x20 54*a47a12beSStefan Roese #define I2C_CR_MTX 0x10 55*a47a12beSStefan Roese #define I2C_CR_TXAK 0x08 56*a47a12beSStefan Roese #define I2C_CR_RSTA 0x04 57*a47a12beSStefan Roese #define I2C_CR_BCST 0x01 58*a47a12beSStefan Roese 59*a47a12beSStefan Roese u8 sr; /* I2C status register */ 60*a47a12beSStefan Roese u8 res3[3]; 61*a47a12beSStefan Roese #define I2C_SR_MCF 0x80 62*a47a12beSStefan Roese #define I2C_SR_MAAS 0x40 63*a47a12beSStefan Roese #define I2C_SR_MBB 0x20 64*a47a12beSStefan Roese #define I2C_SR_MAL 0x10 65*a47a12beSStefan Roese #define I2C_SR_BCSTM 0x08 66*a47a12beSStefan Roese #define I2C_SR_SRW 0x04 67*a47a12beSStefan Roese #define I2C_SR_MIF 0x02 68*a47a12beSStefan Roese #define I2C_SR_RXAK 0x01 69*a47a12beSStefan Roese 70*a47a12beSStefan Roese u8 dr; /* I2C data register */ 71*a47a12beSStefan Roese u8 res4[3]; 72*a47a12beSStefan Roese #define I2C_DR 0xFF 73*a47a12beSStefan Roese #define I2C_DR_SHIFT 0 74*a47a12beSStefan Roese #define I2C_DR_RES ~(I2C_DR) 75*a47a12beSStefan Roese 76*a47a12beSStefan Roese u8 dfsrr; /* I2C digital filter sampling rate register */ 77*a47a12beSStefan Roese u8 res5[3]; 78*a47a12beSStefan Roese #define I2C_DFSRR 0x3F 79*a47a12beSStefan Roese #define I2C_DFSRR_SHIFT 0 80*a47a12beSStefan Roese #define I2C_DFSRR_RES ~(I2C_DR) 81*a47a12beSStefan Roese 82*a47a12beSStefan Roese /* Fill out the reserved block */ 83*a47a12beSStefan Roese u8 res6[0xE8]; 84*a47a12beSStefan Roese } fsl_i2c_t; 85*a47a12beSStefan Roese 86*a47a12beSStefan Roese #endif /* _ASM_I2C_H_ */ 87