1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * Freescale I2C Controller 3a47a12beSStefan Roese * 4a47a12beSStefan Roese * Copyright 2006 Freescale Semiconductor, Inc. 5a47a12beSStefan Roese * 6a47a12beSStefan Roese * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>, 7a47a12beSStefan Roese * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com), 8a47a12beSStefan Roese * and Jeff Brown. 9a47a12beSStefan Roese * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. 10a47a12beSStefan Roese * 11a47a12beSStefan Roese * This software may be used and distributed according to the 12a47a12beSStefan Roese * terms of the GNU Public License, Version 2, incorporated 13a47a12beSStefan Roese * herein by reference. 14a47a12beSStefan Roese * 15a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 16a47a12beSStefan Roese * modify it under the terms of the GNU General Public License 17a47a12beSStefan Roese * Version 2 as published by the Free Software Foundation. 18a47a12beSStefan Roese * 19a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 20a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 21a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22a47a12beSStefan Roese * GNU General Public License for more details. 23a47a12beSStefan Roese * 24a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 25a47a12beSStefan Roese * along with this program; if not, write to the Free Software 26a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27a47a12beSStefan Roese * MA 02111-1307 USA 28a47a12beSStefan Roese */ 29a47a12beSStefan Roese 30a47a12beSStefan Roese #ifndef _ASM_FSL_I2C_H_ 31a47a12beSStefan Roese #define _ASM_FSL_I2C_H_ 32a47a12beSStefan Roese 33a47a12beSStefan Roese #include <asm/types.h> 34a47a12beSStefan Roese 35a47a12beSStefan Roese typedef struct fsl_i2c { 36a47a12beSStefan Roese 37a47a12beSStefan Roese u8 adr; /* I2C slave address */ 38a47a12beSStefan Roese u8 res0[3]; 39a47a12beSStefan Roese #define I2C_ADR 0xFE 40a47a12beSStefan Roese #define I2C_ADR_SHIFT 1 41a47a12beSStefan Roese #define I2C_ADR_RES ~(I2C_ADR) 42a47a12beSStefan Roese 43a47a12beSStefan Roese u8 fdr; /* I2C frequency divider register */ 44a47a12beSStefan Roese u8 res1[3]; 45a47a12beSStefan Roese #define IC2_FDR 0x3F 46a47a12beSStefan Roese #define IC2_FDR_SHIFT 0 47a47a12beSStefan Roese #define IC2_FDR_RES ~(IC2_FDR) 48a47a12beSStefan Roese 49a47a12beSStefan Roese u8 cr; /* I2C control redister */ 50a47a12beSStefan Roese u8 res2[3]; 51a47a12beSStefan Roese #define I2C_CR_MEN 0x80 52a47a12beSStefan Roese #define I2C_CR_MIEN 0x40 53a47a12beSStefan Roese #define I2C_CR_MSTA 0x20 54a47a12beSStefan Roese #define I2C_CR_MTX 0x10 55a47a12beSStefan Roese #define I2C_CR_TXAK 0x08 56a47a12beSStefan Roese #define I2C_CR_RSTA 0x04 57*9c3f77ebSChunhe Lan #define I2C_CR_BIT6 0x02 /* required for workaround A004447 */ 58a47a12beSStefan Roese #define I2C_CR_BCST 0x01 59a47a12beSStefan Roese 60a47a12beSStefan Roese u8 sr; /* I2C status register */ 61a47a12beSStefan Roese u8 res3[3]; 62a47a12beSStefan Roese #define I2C_SR_MCF 0x80 63a47a12beSStefan Roese #define I2C_SR_MAAS 0x40 64a47a12beSStefan Roese #define I2C_SR_MBB 0x20 65a47a12beSStefan Roese #define I2C_SR_MAL 0x10 66a47a12beSStefan Roese #define I2C_SR_BCSTM 0x08 67a47a12beSStefan Roese #define I2C_SR_SRW 0x04 68a47a12beSStefan Roese #define I2C_SR_MIF 0x02 69a47a12beSStefan Roese #define I2C_SR_RXAK 0x01 70a47a12beSStefan Roese 71a47a12beSStefan Roese u8 dr; /* I2C data register */ 72a47a12beSStefan Roese u8 res4[3]; 73a47a12beSStefan Roese #define I2C_DR 0xFF 74a47a12beSStefan Roese #define I2C_DR_SHIFT 0 75a47a12beSStefan Roese #define I2C_DR_RES ~(I2C_DR) 76a47a12beSStefan Roese 77a47a12beSStefan Roese u8 dfsrr; /* I2C digital filter sampling rate register */ 78a47a12beSStefan Roese u8 res5[3]; 79a47a12beSStefan Roese #define I2C_DFSRR 0x3F 80a47a12beSStefan Roese #define I2C_DFSRR_SHIFT 0 81a47a12beSStefan Roese #define I2C_DFSRR_RES ~(I2C_DR) 82a47a12beSStefan Roese 83a47a12beSStefan Roese /* Fill out the reserved block */ 84a47a12beSStefan Roese u8 res6[0xE8]; 85a47a12beSStefan Roese } fsl_i2c_t; 86a47a12beSStefan Roese 87a47a12beSStefan Roese #endif /* _ASM_I2C_H_ */ 88