1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2a47a12beSStefan Roese /* 3a47a12beSStefan Roese * Freescale I2C Controller 4a47a12beSStefan Roese * 5a47a12beSStefan Roese * Copyright 2006 Freescale Semiconductor, Inc. 6a47a12beSStefan Roese * 7a47a12beSStefan Roese * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>, 8a47a12beSStefan Roese * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com), 9a47a12beSStefan Roese * and Jeff Brown. 10a47a12beSStefan Roese * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. 11a47a12beSStefan Roese */ 12a47a12beSStefan Roese 13a47a12beSStefan Roese #ifndef _ASM_FSL_I2C_H_ 14a47a12beSStefan Roese #define _ASM_FSL_I2C_H_ 15a47a12beSStefan Roese 16a47a12beSStefan Roese #include <asm/types.h> 17a47a12beSStefan Roese 18ec2c81c5Smario.six@gdsys.cc typedef struct fsl_i2c_base { 19a47a12beSStefan Roese 20a47a12beSStefan Roese u8 adr; /* I2C slave address */ 21a47a12beSStefan Roese u8 res0[3]; 22a47a12beSStefan Roese #define I2C_ADR 0xFE 23a47a12beSStefan Roese #define I2C_ADR_SHIFT 1 24a47a12beSStefan Roese #define I2C_ADR_RES ~(I2C_ADR) 25a47a12beSStefan Roese 26a47a12beSStefan Roese u8 fdr; /* I2C frequency divider register */ 27a47a12beSStefan Roese u8 res1[3]; 28a47a12beSStefan Roese #define IC2_FDR 0x3F 29a47a12beSStefan Roese #define IC2_FDR_SHIFT 0 30a47a12beSStefan Roese #define IC2_FDR_RES ~(IC2_FDR) 31a47a12beSStefan Roese 32a47a12beSStefan Roese u8 cr; /* I2C control redister */ 33a47a12beSStefan Roese u8 res2[3]; 34a47a12beSStefan Roese #define I2C_CR_MEN 0x80 35a47a12beSStefan Roese #define I2C_CR_MIEN 0x40 36a47a12beSStefan Roese #define I2C_CR_MSTA 0x20 37a47a12beSStefan Roese #define I2C_CR_MTX 0x10 38a47a12beSStefan Roese #define I2C_CR_TXAK 0x08 39a47a12beSStefan Roese #define I2C_CR_RSTA 0x04 409c3f77ebSChunhe Lan #define I2C_CR_BIT6 0x02 /* required for workaround A004447 */ 41a47a12beSStefan Roese #define I2C_CR_BCST 0x01 42a47a12beSStefan Roese 43a47a12beSStefan Roese u8 sr; /* I2C status register */ 44a47a12beSStefan Roese u8 res3[3]; 45a47a12beSStefan Roese #define I2C_SR_MCF 0x80 46a47a12beSStefan Roese #define I2C_SR_MAAS 0x40 47a47a12beSStefan Roese #define I2C_SR_MBB 0x20 48a47a12beSStefan Roese #define I2C_SR_MAL 0x10 49a47a12beSStefan Roese #define I2C_SR_BCSTM 0x08 50a47a12beSStefan Roese #define I2C_SR_SRW 0x04 51a47a12beSStefan Roese #define I2C_SR_MIF 0x02 52a47a12beSStefan Roese #define I2C_SR_RXAK 0x01 53a47a12beSStefan Roese 54a47a12beSStefan Roese u8 dr; /* I2C data register */ 55a47a12beSStefan Roese u8 res4[3]; 56a47a12beSStefan Roese #define I2C_DR 0xFF 57a47a12beSStefan Roese #define I2C_DR_SHIFT 0 58a47a12beSStefan Roese #define I2C_DR_RES ~(I2C_DR) 59a47a12beSStefan Roese 60a47a12beSStefan Roese u8 dfsrr; /* I2C digital filter sampling rate register */ 61a47a12beSStefan Roese u8 res5[3]; 62a47a12beSStefan Roese #define I2C_DFSRR 0x3F 63a47a12beSStefan Roese #define I2C_DFSRR_SHIFT 0 64a47a12beSStefan Roese #define I2C_DFSRR_RES ~(I2C_DR) 65a47a12beSStefan Roese 66a47a12beSStefan Roese /* Fill out the reserved block */ 67a47a12beSStefan Roese u8 res6[0xE8]; 68a47a12beSStefan Roese } fsl_i2c_t; 69a47a12beSStefan Roese 70dbc82ce3Smario.six@gdsys.cc #ifdef CONFIG_DM_I2C 71dbc82ce3Smario.six@gdsys.cc struct fsl_i2c_dev { 72dbc82ce3Smario.six@gdsys.cc struct fsl_i2c_base __iomem *base; /* register base */ 73dbc82ce3Smario.six@gdsys.cc u32 i2c_clk; 74dbc82ce3Smario.six@gdsys.cc u32 index; 75dbc82ce3Smario.six@gdsys.cc u8 slaveadd; 76dbc82ce3Smario.six@gdsys.cc uint speed; 77dbc82ce3Smario.six@gdsys.cc }; 78dbc82ce3Smario.six@gdsys.cc #endif 79dbc82ce3Smario.six@gdsys.cc 80a47a12beSStefan Roese #endif /* _ASM_I2C_H_ */ 81