1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 28 #endif 29 30 /* Number of TLB CAM entries we have on FSL Book-E chips */ 31 #if defined(CONFIG_E500MC) 32 #define CONFIG_SYS_NUM_TLBCAMS 64 33 #elif defined(CONFIG_E500) 34 #define CONFIG_SYS_NUM_TLBCAMS 16 35 #endif 36 37 #if defined(CONFIG_MPC8536) 38 #define CONFIG_MAX_CPUS 1 39 #define CONFIG_SYS_FSL_NUM_LAWS 12 40 #define CONFIG_SYS_FSL_SEC_COMPAT 2 41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 42 43 #elif defined(CONFIG_MPC8540) 44 #define CONFIG_MAX_CPUS 1 45 #define CONFIG_SYS_FSL_NUM_LAWS 8 46 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 47 48 #elif defined(CONFIG_MPC8541) 49 #define CONFIG_MAX_CPUS 1 50 #define CONFIG_SYS_FSL_NUM_LAWS 8 51 #define CONFIG_SYS_FSL_SEC_COMPAT 2 52 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 53 54 #elif defined(CONFIG_MPC8544) 55 #define CONFIG_MAX_CPUS 1 56 #define CONFIG_SYS_FSL_NUM_LAWS 10 57 #define CONFIG_SYS_FSL_SEC_COMPAT 2 58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 59 60 #elif defined(CONFIG_MPC8548) 61 #define CONFIG_MAX_CPUS 1 62 #define CONFIG_SYS_FSL_NUM_LAWS 10 63 #define CONFIG_SYS_FSL_SEC_COMPAT 2 64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 65 66 #elif defined(CONFIG_MPC8555) 67 #define CONFIG_MAX_CPUS 1 68 #define CONFIG_SYS_FSL_NUM_LAWS 8 69 #define CONFIG_SYS_FSL_SEC_COMPAT 2 70 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 71 72 #elif defined(CONFIG_MPC8560) 73 #define CONFIG_MAX_CPUS 1 74 #define CONFIG_SYS_FSL_NUM_LAWS 8 75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 76 77 #elif defined(CONFIG_MPC8568) 78 #define CONFIG_MAX_CPUS 1 79 #define CONFIG_SYS_FSL_NUM_LAWS 10 80 #define CONFIG_SYS_FSL_SEC_COMPAT 2 81 #define QE_MURAM_SIZE 0x10000UL 82 #define MAX_QE_RISC 2 83 #define QE_NUM_OF_SNUM 28 84 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 85 86 #elif defined(CONFIG_MPC8569) 87 #define CONFIG_MAX_CPUS 1 88 #define CONFIG_SYS_FSL_NUM_LAWS 10 89 #define CONFIG_SYS_FSL_SEC_COMPAT 2 90 #define QE_MURAM_SIZE 0x20000UL 91 #define MAX_QE_RISC 4 92 #define QE_NUM_OF_SNUM 46 93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 94 95 #elif defined(CONFIG_MPC8572) 96 #define CONFIG_MAX_CPUS 2 97 #define CONFIG_SYS_FSL_NUM_LAWS 12 98 #define CONFIG_SYS_FSL_SEC_COMPAT 2 99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 100 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 101 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 102 103 #elif defined(CONFIG_P1010) 104 #define CONFIG_MAX_CPUS 1 105 #define CONFIG_FSL_SDHC_V2_3 106 #define CONFIG_SYS_FSL_NUM_LAWS 12 107 #define CONFIG_TSECV2 108 #define CONFIG_SYS_FSL_SEC_COMPAT 4 109 #define CONFIG_FSL_SATA_V2 110 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 111 #define CONFIG_NUM_DDR_CONTROLLERS 1 112 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 113 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 114 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 115 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 116 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 117 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 118 119 /* P1011 is single core version of P1020 */ 120 #elif defined(CONFIG_P1011) 121 #define CONFIG_MAX_CPUS 1 122 #define CONFIG_SYS_FSL_NUM_LAWS 12 123 #define CONFIG_TSECV2 124 #define CONFIG_FSL_PCIE_DISABLE_ASPM 125 #define CONFIG_SYS_FSL_SEC_COMPAT 2 126 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 127 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 128 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 129 130 /* P1012 is single core version of P1021 */ 131 #elif defined(CONFIG_P1012) 132 #define CONFIG_MAX_CPUS 1 133 #define CONFIG_SYS_FSL_NUM_LAWS 12 134 #define CONFIG_TSECV2 135 #define CONFIG_FSL_PCIE_DISABLE_ASPM 136 #define CONFIG_SYS_FSL_SEC_COMPAT 2 137 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 138 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 139 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 140 #define QE_MURAM_SIZE 0x6000UL 141 #define MAX_QE_RISC 1 142 #define QE_NUM_OF_SNUM 28 143 144 /* P1013 is single core version of P1022 */ 145 #elif defined(CONFIG_P1013) 146 #define CONFIG_MAX_CPUS 1 147 #define CONFIG_SYS_FSL_NUM_LAWS 12 148 #define CONFIG_TSECV2 149 #define CONFIG_SYS_FSL_SEC_COMPAT 2 150 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 151 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 152 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 153 #define CONFIG_FSL_SATA_ERRATUM_A001 154 155 #elif defined(CONFIG_P1014) 156 #define CONFIG_MAX_CPUS 1 157 #define CONFIG_FSL_SDHC_V2_3 158 #define CONFIG_SYS_FSL_NUM_LAWS 12 159 #define CONFIG_TSECV2 160 #define CONFIG_SYS_FSL_SEC_COMPAT 4 161 #define CONFIG_FSL_SATA_V2 162 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 163 #define CONFIG_NUM_DDR_CONTROLLERS 1 164 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 165 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 166 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 167 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 168 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 169 170 /* P1015 is single core version of P1024 */ 171 #elif defined(CONFIG_P1015) 172 #define CONFIG_MAX_CPUS 1 173 #define CONFIG_SYS_FSL_NUM_LAWS 12 174 #define CONFIG_TSECV2 175 #define CONFIG_FSL_PCIE_DISABLE_ASPM 176 #define CONFIG_SYS_FSL_SEC_COMPAT 2 177 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 178 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 179 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 180 181 /* P1016 is single core version of P1025 */ 182 #elif defined(CONFIG_P1016) 183 #define CONFIG_MAX_CPUS 1 184 #define CONFIG_SYS_FSL_NUM_LAWS 12 185 #define CONFIG_TSECV2 186 #define CONFIG_FSL_PCIE_DISABLE_ASPM 187 #define CONFIG_SYS_FSL_SEC_COMPAT 2 188 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 189 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 190 #define QE_MURAM_SIZE 0x6000UL 191 #define MAX_QE_RISC 1 192 #define QE_NUM_OF_SNUM 28 193 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 194 195 /* P1017 is single core version of P1023 */ 196 #elif defined(CONFIG_P1017) 197 #define CONFIG_MAX_CPUS 1 198 #define CONFIG_SYS_FSL_NUM_LAWS 12 199 #define CONFIG_SYS_FSL_SEC_COMPAT 4 200 #define CONFIG_SYS_NUM_FMAN 1 201 #define CONFIG_SYS_NUM_FM1_DTSEC 2 202 #define CONFIG_NUM_DDR_CONTROLLERS 1 203 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 204 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 205 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 206 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 207 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 208 209 #elif defined(CONFIG_P1020) 210 #define CONFIG_MAX_CPUS 2 211 #define CONFIG_SYS_FSL_NUM_LAWS 12 212 #define CONFIG_TSECV2 213 #define CONFIG_FSL_PCIE_DISABLE_ASPM 214 #define CONFIG_SYS_FSL_SEC_COMPAT 2 215 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 216 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 217 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 218 219 #elif defined(CONFIG_P1021) 220 #define CONFIG_MAX_CPUS 2 221 #define CONFIG_SYS_FSL_NUM_LAWS 12 222 #define CONFIG_TSECV2 223 #define CONFIG_FSL_PCIE_DISABLE_ASPM 224 #define CONFIG_SYS_FSL_SEC_COMPAT 2 225 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 226 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 227 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 228 #define QE_MURAM_SIZE 0x6000UL 229 #define MAX_QE_RISC 1 230 #define QE_NUM_OF_SNUM 28 231 232 #elif defined(CONFIG_P1022) 233 #define CONFIG_MAX_CPUS 2 234 #define CONFIG_SYS_FSL_NUM_LAWS 12 235 #define CONFIG_TSECV2 236 #define CONFIG_SYS_FSL_SEC_COMPAT 2 237 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 238 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 239 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 240 #define CONFIG_FSL_SATA_ERRATUM_A001 241 242 #elif defined(CONFIG_P1023) 243 #define CONFIG_MAX_CPUS 2 244 #define CONFIG_SYS_FSL_NUM_LAWS 12 245 #define CONFIG_SYS_FSL_SEC_COMPAT 4 246 #define CONFIG_SYS_NUM_FMAN 1 247 #define CONFIG_SYS_NUM_FM1_DTSEC 2 248 #define CONFIG_NUM_DDR_CONTROLLERS 1 249 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 250 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 251 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 252 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 253 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 254 255 /* P1024 is lower end variant of P1020 */ 256 #elif defined(CONFIG_P1024) 257 #define CONFIG_MAX_CPUS 2 258 #define CONFIG_SYS_FSL_NUM_LAWS 12 259 #define CONFIG_TSECV2 260 #define CONFIG_FSL_PCIE_DISABLE_ASPM 261 #define CONFIG_SYS_FSL_SEC_COMPAT 2 262 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 263 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 264 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 265 266 /* P1025 is lower end variant of P1021 */ 267 #elif defined(CONFIG_P1025) 268 #define CONFIG_MAX_CPUS 2 269 #define CONFIG_SYS_FSL_NUM_LAWS 12 270 #define CONFIG_TSECV2 271 #define CONFIG_FSL_PCIE_DISABLE_ASPM 272 #define CONFIG_SYS_FSL_SEC_COMPAT 2 273 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 274 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 275 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 276 #define QE_MURAM_SIZE 0x6000UL 277 #define MAX_QE_RISC 1 278 #define QE_NUM_OF_SNUM 28 279 280 /* P2010 is single core version of P2020 */ 281 #elif defined(CONFIG_P2010) 282 #define CONFIG_MAX_CPUS 1 283 #define CONFIG_SYS_FSL_NUM_LAWS 12 284 #define CONFIG_SYS_FSL_SEC_COMPAT 2 285 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 286 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 287 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 288 289 #elif defined(CONFIG_P2020) 290 #define CONFIG_MAX_CPUS 2 291 #define CONFIG_SYS_FSL_NUM_LAWS 12 292 #define CONFIG_SYS_FSL_SEC_COMPAT 2 293 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 294 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 295 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 296 297 #elif defined(CONFIG_PPC_P2040) 298 #define CONFIG_MAX_CPUS 4 299 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 300 #define CONFIG_SYS_FSL_NUM_LAWS 32 301 #define CONFIG_SYS_FSL_SEC_COMPAT 4 302 #define CONFIG_SYS_NUM_FMAN 1 303 #define CONFIG_SYS_NUM_FM1_DTSEC 5 304 #define CONFIG_NUM_DDR_CONTROLLERS 1 305 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 306 #define CONFIG_SYS_FSL_TBCLK_DIV 32 307 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 308 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 309 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 310 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 311 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 312 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 313 314 #elif defined(CONFIG_PPC_P2041) 315 #define CONFIG_MAX_CPUS 4 316 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 317 #define CONFIG_SYS_FSL_NUM_LAWS 32 318 #define CONFIG_SYS_FSL_SEC_COMPAT 4 319 #define CONFIG_SYS_NUM_FMAN 1 320 #define CONFIG_SYS_NUM_FM1_DTSEC 5 321 #define CONFIG_SYS_NUM_FM1_10GEC 1 322 #define CONFIG_NUM_DDR_CONTROLLERS 1 323 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 324 #define CONFIG_SYS_FSL_TBCLK_DIV 32 325 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 326 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 327 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 328 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 329 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 330 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 331 332 #elif defined(CONFIG_PPC_P3041) 333 #define CONFIG_MAX_CPUS 4 334 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 335 #define CONFIG_SYS_FSL_NUM_LAWS 32 336 #define CONFIG_SYS_FSL_SEC_COMPAT 4 337 #define CONFIG_SYS_NUM_FMAN 1 338 #define CONFIG_SYS_NUM_FM1_DTSEC 5 339 #define CONFIG_SYS_NUM_FM1_10GEC 1 340 #define CONFIG_NUM_DDR_CONTROLLERS 1 341 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 342 #define CONFIG_SYS_FSL_TBCLK_DIV 32 343 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 344 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 345 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 346 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 347 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 348 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 349 350 #elif defined(CONFIG_PPC_P4040) 351 #define CONFIG_MAX_CPUS 4 352 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 353 #define CONFIG_SYS_FSL_NUM_LAWS 32 354 #define CONFIG_SYS_FSL_SEC_COMPAT 4 355 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 356 #define CONFIG_SYS_FSL_TBCLK_DIV 16 357 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 358 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 359 360 #elif defined(CONFIG_PPC_P4080) 361 #define CONFIG_MAX_CPUS 8 362 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 363 #define CONFIG_SYS_FSL_NUM_LAWS 32 364 #define CONFIG_SYS_FSL_SEC_COMPAT 4 365 #define CONFIG_SYS_NUM_FMAN 2 366 #define CONFIG_SYS_NUM_FM1_DTSEC 4 367 #define CONFIG_SYS_NUM_FM2_DTSEC 4 368 #define CONFIG_SYS_NUM_FM1_10GEC 1 369 #define CONFIG_SYS_NUM_FM2_10GEC 1 370 #define CONFIG_NUM_DDR_CONTROLLERS 2 371 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 372 #define CONFIG_SYS_FSL_TBCLK_DIV 16 373 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 374 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 375 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 376 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 377 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 378 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 379 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 380 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 381 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 382 #define CONFIG_SYS_P4080_ERRATUM_CPU22 383 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 384 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 385 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 386 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 387 388 /* P5010 is single core version of P5020 */ 389 #elif defined(CONFIG_PPC_P5010) 390 #define CONFIG_MAX_CPUS 1 391 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 392 #define CONFIG_SYS_FSL_NUM_LAWS 32 393 #define CONFIG_SYS_FSL_SEC_COMPAT 4 394 #define CONFIG_SYS_NUM_FMAN 1 395 #define CONFIG_SYS_NUM_FM1_DTSEC 5 396 #define CONFIG_SYS_NUM_FM1_10GEC 1 397 #define CONFIG_NUM_DDR_CONTROLLERS 1 398 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 399 #define CONFIG_SYS_FSL_TBCLK_DIV 32 400 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 401 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 402 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 403 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 404 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 405 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 406 407 #elif defined(CONFIG_PPC_P5020) 408 #define CONFIG_MAX_CPUS 2 409 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 410 #define CONFIG_SYS_FSL_NUM_LAWS 32 411 #define CONFIG_SYS_FSL_SEC_COMPAT 4 412 #define CONFIG_SYS_NUM_FMAN 1 413 #define CONFIG_SYS_NUM_FM1_DTSEC 5 414 #define CONFIG_SYS_NUM_FM1_10GEC 1 415 #define CONFIG_NUM_DDR_CONTROLLERS 2 416 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 417 #define CONFIG_SYS_FSL_TBCLK_DIV 32 418 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 419 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 420 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 421 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 422 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 423 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 424 425 #else 426 #error Processor type not defined for this platform 427 #endif 428 429 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 430 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 431 #endif 432 433 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 434