1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #define FSL_DDR_VER_4_7 47 23 #define FSL_DDR_VER_5_0 50 24 25 /* Number of TLB CAM entries we have on FSL Book-E chips */ 26 #if defined(CONFIG_E500MC) 27 #define CONFIG_SYS_NUM_TLBCAMS 64 28 #elif defined(CONFIG_E500) 29 #define CONFIG_SYS_NUM_TLBCAMS 16 30 #endif 31 32 #if defined(CONFIG_MPC8536) 33 #define CONFIG_MAX_CPUS 1 34 #define CONFIG_SYS_FSL_NUM_LAWS 12 35 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 36 #define CONFIG_SYS_FSL_SEC_COMPAT 2 37 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 38 #define CONFIG_SYS_FSL_ERRATUM_A005125 39 40 #elif defined(CONFIG_MPC8540) 41 #define CONFIG_MAX_CPUS 1 42 #define CONFIG_SYS_FSL_NUM_LAWS 8 43 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 44 45 #elif defined(CONFIG_MPC8541) 46 #define CONFIG_MAX_CPUS 1 47 #define CONFIG_SYS_FSL_NUM_LAWS 8 48 #define CONFIG_SYS_FSL_SEC_COMPAT 2 49 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 50 51 #elif defined(CONFIG_MPC8544) 52 #define CONFIG_MAX_CPUS 1 53 #define CONFIG_SYS_FSL_NUM_LAWS 10 54 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 55 #define CONFIG_SYS_FSL_SEC_COMPAT 2 56 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 57 #define CONFIG_SYS_FSL_ERRATUM_A005125 58 59 #elif defined(CONFIG_MPC8548) 60 #define CONFIG_MAX_CPUS 1 61 #define CONFIG_SYS_FSL_NUM_LAWS 10 62 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 63 #define CONFIG_SYS_FSL_SEC_COMPAT 2 64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 65 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 66 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 67 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 68 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 69 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 70 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 71 #define CONFIG_SYS_FSL_RMU 72 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 73 #define CONFIG_SYS_FSL_ERRATUM_A005125 74 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 75 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 76 77 #elif defined(CONFIG_MPC8555) 78 #define CONFIG_MAX_CPUS 1 79 #define CONFIG_SYS_FSL_NUM_LAWS 8 80 #define CONFIG_SYS_FSL_SEC_COMPAT 2 81 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 82 83 #elif defined(CONFIG_MPC8560) 84 #define CONFIG_MAX_CPUS 1 85 #define CONFIG_SYS_FSL_NUM_LAWS 8 86 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 87 88 #elif defined(CONFIG_MPC8568) 89 #define CONFIG_MAX_CPUS 1 90 #define CONFIG_SYS_FSL_NUM_LAWS 10 91 #define CONFIG_SYS_FSL_SEC_COMPAT 2 92 #define QE_MURAM_SIZE 0x10000UL 93 #define MAX_QE_RISC 2 94 #define QE_NUM_OF_SNUM 28 95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 96 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 97 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 98 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 99 #define CONFIG_SYS_FSL_RMU 100 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 101 102 #elif defined(CONFIG_MPC8569) 103 #define CONFIG_MAX_CPUS 1 104 #define CONFIG_SYS_FSL_NUM_LAWS 10 105 #define CONFIG_SYS_FSL_SEC_COMPAT 2 106 #define QE_MURAM_SIZE 0x20000UL 107 #define MAX_QE_RISC 4 108 #define QE_NUM_OF_SNUM 46 109 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 110 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 111 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 112 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 113 #define CONFIG_SYS_FSL_RMU 114 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 115 #define CONFIG_SYS_FSL_ERRATUM_A005125 116 117 #elif defined(CONFIG_MPC8572) 118 #define CONFIG_MAX_CPUS 2 119 #define CONFIG_SYS_FSL_NUM_LAWS 12 120 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 121 #define CONFIG_SYS_FSL_SEC_COMPAT 2 122 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 123 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 124 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 125 #define CONFIG_SYS_FSL_ERRATUM_A005125 126 127 #elif defined(CONFIG_P1010) 128 #define CONFIG_MAX_CPUS 1 129 #define CONFIG_FSL_SDHC_V2_3 130 #define CONFIG_SYS_FSL_NUM_LAWS 12 131 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 132 #define CONFIG_TSECV2 133 #define CONFIG_SYS_FSL_SEC_COMPAT 4 134 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 135 #define CONFIG_NUM_DDR_CONTROLLERS 1 136 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 137 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 138 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 139 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 140 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 141 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 142 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 143 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 144 #define CONFIG_SYS_FSL_ERRATUM_A005125 145 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 146 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 147 148 /* P1011 is single core version of P1020 */ 149 #elif defined(CONFIG_P1011) 150 #define CONFIG_MAX_CPUS 1 151 #define CONFIG_SYS_FSL_NUM_LAWS 12 152 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 153 #define CONFIG_TSECV2 154 #define CONFIG_FSL_PCIE_DISABLE_ASPM 155 #define CONFIG_SYS_FSL_SEC_COMPAT 2 156 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 157 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 158 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 159 #define CONFIG_SYS_FSL_ERRATUM_A005125 160 161 /* P1012 is single core version of P1021 */ 162 #elif defined(CONFIG_P1012) 163 #define CONFIG_MAX_CPUS 1 164 #define CONFIG_SYS_FSL_NUM_LAWS 12 165 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 166 #define CONFIG_TSECV2 167 #define CONFIG_FSL_PCIE_DISABLE_ASPM 168 #define CONFIG_SYS_FSL_SEC_COMPAT 2 169 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 170 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 171 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 172 #define QE_MURAM_SIZE 0x6000UL 173 #define MAX_QE_RISC 1 174 #define QE_NUM_OF_SNUM 28 175 #define CONFIG_SYS_FSL_ERRATUM_A005125 176 177 /* P1013 is single core version of P1022 */ 178 #elif defined(CONFIG_P1013) 179 #define CONFIG_MAX_CPUS 1 180 #define CONFIG_SYS_FSL_NUM_LAWS 12 181 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 182 #define CONFIG_TSECV2 183 #define CONFIG_SYS_FSL_SEC_COMPAT 2 184 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 185 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 187 #define CONFIG_FSL_SATA_ERRATUM_A001 188 #define CONFIG_SYS_FSL_ERRATUM_A005125 189 190 #elif defined(CONFIG_P1014) 191 #define CONFIG_MAX_CPUS 1 192 #define CONFIG_FSL_SDHC_V2_3 193 #define CONFIG_SYS_FSL_NUM_LAWS 12 194 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 195 #define CONFIG_TSECV2 196 #define CONFIG_SYS_FSL_SEC_COMPAT 4 197 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 198 #define CONFIG_NUM_DDR_CONTROLLERS 1 199 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 200 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 201 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 202 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 203 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 204 205 /* P1017 is single core version of P1023 */ 206 #elif defined(CONFIG_P1017) 207 #define CONFIG_MAX_CPUS 1 208 #define CONFIG_SYS_FSL_NUM_LAWS 12 209 #define CONFIG_SYS_FSL_SEC_COMPAT 4 210 #define CONFIG_SYS_NUM_FMAN 1 211 #define CONFIG_SYS_NUM_FM1_DTSEC 2 212 #define CONFIG_NUM_DDR_CONTROLLERS 1 213 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 214 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 215 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 216 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 217 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 218 #define CONFIG_SYS_FSL_ERRATUM_A005125 219 220 #elif defined(CONFIG_P1020) 221 #define CONFIG_MAX_CPUS 2 222 #define CONFIG_SYS_FSL_NUM_LAWS 12 223 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 224 #define CONFIG_TSECV2 225 #define CONFIG_FSL_PCIE_DISABLE_ASPM 226 #define CONFIG_SYS_FSL_SEC_COMPAT 2 227 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 228 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 229 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 230 #define CONFIG_SYS_FSL_ERRATUM_A005125 231 232 #elif defined(CONFIG_P1021) 233 #define CONFIG_MAX_CPUS 2 234 #define CONFIG_SYS_FSL_NUM_LAWS 12 235 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 236 #define CONFIG_TSECV2 237 #define CONFIG_FSL_PCIE_DISABLE_ASPM 238 #define CONFIG_SYS_FSL_SEC_COMPAT 2 239 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 240 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 241 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 242 #define QE_MURAM_SIZE 0x6000UL 243 #define MAX_QE_RISC 1 244 #define QE_NUM_OF_SNUM 28 245 #define CONFIG_SYS_FSL_ERRATUM_A005125 246 247 #elif defined(CONFIG_P1022) 248 #define CONFIG_MAX_CPUS 2 249 #define CONFIG_SYS_FSL_NUM_LAWS 12 250 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 251 #define CONFIG_TSECV2 252 #define CONFIG_SYS_FSL_SEC_COMPAT 2 253 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 254 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 255 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 256 #define CONFIG_FSL_SATA_ERRATUM_A001 257 #define CONFIG_SYS_FSL_ERRATUM_A005125 258 259 #elif defined(CONFIG_P1023) 260 #define CONFIG_MAX_CPUS 2 261 #define CONFIG_SYS_FSL_NUM_LAWS 12 262 #define CONFIG_SYS_FSL_SEC_COMPAT 4 263 #define CONFIG_SYS_NUM_FMAN 1 264 #define CONFIG_SYS_NUM_FM1_DTSEC 2 265 #define CONFIG_NUM_DDR_CONTROLLERS 1 266 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 267 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 268 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 269 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 270 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 271 #define CONFIG_SYS_FSL_ERRATUM_A005125 272 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 273 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 274 275 /* P1024 is lower end variant of P1020 */ 276 #elif defined(CONFIG_P1024) 277 #define CONFIG_MAX_CPUS 2 278 #define CONFIG_SYS_FSL_NUM_LAWS 12 279 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 280 #define CONFIG_TSECV2 281 #define CONFIG_FSL_PCIE_DISABLE_ASPM 282 #define CONFIG_SYS_FSL_SEC_COMPAT 2 283 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 284 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 285 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 286 #define CONFIG_SYS_FSL_ERRATUM_A005125 287 288 /* P1025 is lower end variant of P1021 */ 289 #elif defined(CONFIG_P1025) 290 #define CONFIG_MAX_CPUS 2 291 #define CONFIG_SYS_FSL_NUM_LAWS 12 292 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 293 #define CONFIG_TSECV2 294 #define CONFIG_FSL_PCIE_DISABLE_ASPM 295 #define CONFIG_SYS_FSL_SEC_COMPAT 2 296 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 297 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 298 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 299 #define QE_MURAM_SIZE 0x6000UL 300 #define MAX_QE_RISC 1 301 #define QE_NUM_OF_SNUM 28 302 #define CONFIG_SYS_FSL_ERRATUM_A005125 303 304 /* P2010 is single core version of P2020 */ 305 #elif defined(CONFIG_P2010) 306 #define CONFIG_MAX_CPUS 1 307 #define CONFIG_SYS_FSL_NUM_LAWS 12 308 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 309 #define CONFIG_SYS_FSL_SEC_COMPAT 2 310 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 311 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 312 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 313 #define CONFIG_SYS_FSL_ERRATUM_A005125 314 315 #elif defined(CONFIG_P2020) 316 #define CONFIG_MAX_CPUS 2 317 #define CONFIG_SYS_FSL_NUM_LAWS 12 318 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 319 #define CONFIG_SYS_FSL_SEC_COMPAT 2 320 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 321 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 322 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 323 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 324 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 325 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 326 #define CONFIG_SYS_FSL_RMU 327 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 328 #define CONFIG_SYS_FSL_ERRATUM_A005125 329 330 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 331 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 332 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 333 #define CONFIG_MAX_CPUS 4 334 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 335 #define CONFIG_SYS_FSL_NUM_LAWS 32 336 #define CONFIG_SYS_FSL_SEC_COMPAT 4 337 #define CONFIG_SYS_NUM_FMAN 1 338 #define CONFIG_SYS_NUM_FM1_DTSEC 5 339 #define CONFIG_SYS_NUM_FM1_10GEC 1 340 #define CONFIG_NUM_DDR_CONTROLLERS 1 341 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 342 #define CONFIG_SYS_FSL_TBCLK_DIV 32 343 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 344 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 345 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 346 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 347 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 348 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 349 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 350 #define CONFIG_SYS_FSL_ERRATUM_USB14 351 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 352 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 353 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 354 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 355 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 356 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 357 #define CONFIG_SYS_FSL_ERRATUM_A004510 358 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 359 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 360 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 361 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 362 #define CONFIG_SYS_FSL_ERRATUM_A004849 363 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 364 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 365 366 #elif defined(CONFIG_PPC_P3041) 367 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 368 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 369 #define CONFIG_MAX_CPUS 4 370 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 371 #define CONFIG_SYS_FSL_NUM_LAWS 32 372 #define CONFIG_SYS_FSL_SEC_COMPAT 4 373 #define CONFIG_SYS_NUM_FMAN 1 374 #define CONFIG_SYS_NUM_FM1_DTSEC 5 375 #define CONFIG_SYS_NUM_FM1_10GEC 1 376 #define CONFIG_NUM_DDR_CONTROLLERS 1 377 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 378 #define CONFIG_SYS_FSL_TBCLK_DIV 32 379 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 380 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 381 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 382 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 383 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 384 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 385 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 386 #define CONFIG_SYS_FSL_ERRATUM_USB14 387 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 388 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 389 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 390 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 391 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 392 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 393 #define CONFIG_SYS_FSL_ERRATUM_A004510 394 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 395 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 396 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 397 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 398 #define CONFIG_SYS_FSL_ERRATUM_A004849 399 #define CONFIG_SYS_FSL_ERRATUM_A005812 400 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 401 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 402 403 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 404 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 405 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 406 #define CONFIG_MAX_CPUS 8 407 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 408 #define CONFIG_SYS_FSL_NUM_LAWS 32 409 #define CONFIG_SYS_FSL_SEC_COMPAT 4 410 #define CONFIG_SYS_NUM_FMAN 2 411 #define CONFIG_SYS_NUM_FM1_DTSEC 4 412 #define CONFIG_SYS_NUM_FM2_DTSEC 4 413 #define CONFIG_SYS_NUM_FM1_10GEC 1 414 #define CONFIG_SYS_NUM_FM2_10GEC 1 415 #define CONFIG_NUM_DDR_CONTROLLERS 2 416 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 417 #define CONFIG_SYS_FSL_TBCLK_DIV 16 418 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 419 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 420 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 421 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 422 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 423 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 424 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 425 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 426 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 427 #define CONFIG_SYS_P4080_ERRATUM_CPU22 428 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 429 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 430 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 431 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 432 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 433 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 434 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 435 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 436 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 437 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 438 #define CONFIG_SYS_FSL_RMU 439 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 440 #define CONFIG_SYS_FSL_ERRATUM_A004510 441 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 442 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 443 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 444 #define CONFIG_SYS_FSL_ERRATUM_A004849 445 #define CONFIG_SYS_FSL_ERRATUM_A004580 446 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 447 #define CONFIG_SYS_FSL_ERRATUM_A005812 448 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 449 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 450 451 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 452 #define CONFIG_SYS_PPC64 /* 64-bit core */ 453 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 454 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 455 #define CONFIG_MAX_CPUS 2 456 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 457 #define CONFIG_SYS_FSL_NUM_LAWS 32 458 #define CONFIG_SYS_FSL_SEC_COMPAT 4 459 #define CONFIG_SYS_NUM_FMAN 1 460 #define CONFIG_SYS_NUM_FM1_DTSEC 5 461 #define CONFIG_SYS_NUM_FM1_10GEC 1 462 #define CONFIG_NUM_DDR_CONTROLLERS 2 463 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 464 #define CONFIG_SYS_FSL_TBCLK_DIV 32 465 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 466 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 467 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 468 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 469 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 470 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 471 #define CONFIG_SYS_FSL_ERRATUM_USB14 472 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 473 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 474 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 475 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 476 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 477 #define CONFIG_SYS_FSL_ERRATUM_A004510 478 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 479 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 480 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 481 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 482 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 483 484 #elif defined(CONFIG_PPC_P5040) 485 #define CONFIG_SYS_PPC64 486 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 487 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 488 #define CONFIG_MAX_CPUS 4 489 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 490 #define CONFIG_SYS_FSL_NUM_LAWS 32 491 #define CONFIG_SYS_FSL_SEC_COMPAT 4 492 #define CONFIG_SYS_NUM_FMAN 2 493 #define CONFIG_SYS_NUM_FM1_DTSEC 5 494 #define CONFIG_SYS_NUM_FM1_10GEC 1 495 #define CONFIG_SYS_NUM_FM2_DTSEC 5 496 #define CONFIG_SYS_NUM_FM2_10GEC 1 497 #define CONFIG_NUM_DDR_CONTROLLERS 2 498 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 499 #define CONFIG_SYS_FSL_TBCLK_DIV 16 500 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 501 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 502 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 503 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 504 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 505 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 506 #define CONFIG_SYS_FSL_ERRATUM_USB14 507 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 508 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 509 #define CONFIG_SYS_FSL_ERRATUM_A004699 510 #define CONFIG_SYS_FSL_ERRATUM_A004510 511 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 512 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 513 #define CONFIG_SYS_FSL_ERRATUM_A005812 514 515 #elif defined(CONFIG_BSC9131) 516 #define CONFIG_MAX_CPUS 1 517 #define CONFIG_FSL_SDHC_V2_3 518 #define CONFIG_SYS_FSL_NUM_LAWS 12 519 #define CONFIG_TSECV2 520 #define CONFIG_SYS_FSL_SEC_COMPAT 4 521 #define CONFIG_NUM_DDR_CONTROLLERS 1 522 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 523 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 524 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 525 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 526 #define CONFIG_NAND_FSL_IFC 527 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 528 #define CONFIG_SYS_FSL_ERRATUM_A005125 529 530 #elif defined(CONFIG_BSC9132) 531 #define CONFIG_MAX_CPUS 2 532 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 533 #define CONFIG_FSL_SDHC_V2_3 534 #define CONFIG_SYS_FSL_NUM_LAWS 12 535 #define CONFIG_TSECV2 536 #define CONFIG_SYS_FSL_SEC_COMPAT 4 537 #define CONFIG_NUM_DDR_CONTROLLERS 2 538 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 539 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 540 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 541 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 542 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 543 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 544 #define CONFIG_NAND_FSL_IFC 545 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 546 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 547 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 548 #define CONFIG_SYS_FSL_ERRATUM_A005125 549 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 550 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 551 552 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 553 #define CONFIG_E6500 554 #define CONFIG_SYS_PPC64 /* 64-bit core */ 555 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 556 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 557 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 558 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 559 #ifdef CONFIG_PPC_T4240 560 #define CONFIG_MAX_CPUS 12 561 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 562 #define CONFIG_SYS_NUM_FM1_DTSEC 8 563 #define CONFIG_SYS_NUM_FM1_10GEC 2 564 #define CONFIG_SYS_NUM_FM2_DTSEC 8 565 #define CONFIG_SYS_NUM_FM2_10GEC 2 566 #define CONFIG_NUM_DDR_CONTROLLERS 3 567 #else 568 #define CONFIG_MAX_CPUS 8 569 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 570 #define CONFIG_SYS_NUM_FM1_DTSEC 7 571 #define CONFIG_SYS_NUM_FM1_10GEC 1 572 #define CONFIG_SYS_NUM_FM2_DTSEC 7 573 #define CONFIG_SYS_NUM_FM2_10GEC 1 574 #define CONFIG_NUM_DDR_CONTROLLERS 2 575 #endif 576 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 577 #define CONFIG_SYS_FSL_NUM_LAWS 32 578 #define CONFIG_SYS_FSL_SRDS_1 579 #define CONFIG_SYS_FSL_SRDS_2 580 #define CONFIG_SYS_FSL_SRDS_3 581 #define CONFIG_SYS_FSL_SRDS_4 582 #define CONFIG_SYS_FSL_SEC_COMPAT 4 583 #define CONFIG_SYS_NUM_FMAN 2 584 #define CONFIG_SYS_PME_CLK 0 585 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 586 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 587 #define CONFIG_SYS_FMAN_V3 588 #define CONFIG_SYS_FM1_CLK 3 589 #define CONFIG_SYS_FM2_CLK 3 590 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 591 #define CONFIG_SYS_FSL_TBCLK_DIV 16 592 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 593 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 594 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 595 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 596 #define CONFIG_SYS_FSL_SRIO_LIODN 597 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 598 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 599 #define CONFIG_SYS_FSL_ERRATUM_A004468 600 #define CONFIG_SYS_FSL_ERRATUM_A_004934 601 #define CONFIG_SYS_FSL_ERRATUM_A005871 602 #define CONFIG_SYS_FSL_ERRATUM_A006593 603 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 604 #define CONFIG_SYS_FSL_PCI_VER_3_X 605 606 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 607 #define CONFIG_E6500 608 #define CONFIG_SYS_PPC64 /* 64-bit core */ 609 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 610 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 611 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 612 #define CONFIG_SYS_FSL_NUM_LAWS 32 613 #define CONFIG_SYS_FSL_SRDS_1 614 #define CONFIG_SYS_FSL_SRDS_2 615 #define CONFIG_SYS_FSL_SEC_COMPAT 4 616 #define CONFIG_SYS_NUM_FMAN 1 617 #define CONFIG_SYS_FM1_CLK 0 618 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 619 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 620 #define CONFIG_SYS_FMAN_V3 621 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 622 #define CONFIG_SYS_FSL_TBCLK_DIV 16 623 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 624 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 625 #define CONFIG_SYS_FSL_ERRATUM_A_004934 626 #define CONFIG_SYS_FSL_ERRATUM_A005871 627 #define CONFIG_SYS_FSL_ERRATUM_A006593 628 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 629 630 #ifdef CONFIG_PPC_B4860 631 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 632 #define CONFIG_MAX_CPUS 4 633 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 634 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 635 #define CONFIG_SYS_NUM_FM1_DTSEC 6 636 #define CONFIG_SYS_NUM_FM1_10GEC 2 637 #define CONFIG_NUM_DDR_CONTROLLERS 2 638 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 639 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 640 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 641 #define CONFIG_SYS_FSL_SRIO_LIODN 642 #else 643 #define CONFIG_MAX_CPUS 2 644 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 645 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 646 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 647 #define CONFIG_SYS_NUM_FM1_DTSEC 4 648 #define CONFIG_SYS_NUM_FM1_10GEC 0 649 #define CONFIG_NUM_DDR_CONTROLLERS 1 650 #endif 651 652 #elif defined(CONFIG_PPC_T1040) 653 #define CONFIG_E5500 654 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 655 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 656 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 657 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 658 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 659 #define CONFIG_MAX_CPUS 4 660 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 661 #define CONFIG_MAX_CPUS 2 662 #endif 663 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 664 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 665 #define CONFIG_SYS_SDHC_CLOCK 0 666 #define CONFIG_SYS_FSL_NUM_LAWS 16 667 #define CONFIG_SYS_FSL_SRDS_1 668 #define CONFIG_SYS_FSL_SEC_COMPAT 5 669 #define CONFIG_SYS_NUM_FMAN 1 670 #define CONFIG_SYS_NUM_FM1_DTSEC 5 671 #define CONFIG_NUM_DDR_CONTROLLERS 1 672 #define CONFIG_PME_PLAT_CLK_DIV 2 673 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 674 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 675 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 676 #define CONFIG_SYS_FMAN_V3 677 #define CONFIG_FM_PLAT_CLK_DIV 1 678 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 679 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 680 #define CONFIG_SYS_FSL_TBCLK_DIV 32 681 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 682 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 683 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 684 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 685 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 686 687 #elif defined(CONFIG_PPC_C29X) 688 #define CONFIG_MAX_CPUS 1 689 #define CONFIG_FSL_SDHC_V2_3 690 #define CONFIG_SYS_FSL_NUM_LAWS 12 691 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 692 #define CONFIG_TSECV2_1 693 #define CONFIG_SYS_FSL_SEC_COMPAT 6 694 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 695 #define CONFIG_NUM_DDR_CONTROLLERS 1 696 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 697 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 698 #define CONFIG_SYS_FSL_ERRATUM_A005125 699 700 #else 701 #error Processor type not defined for this platform 702 #endif 703 704 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 705 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 706 #endif 707 708 #ifdef CONFIG_E6500 709 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 710 #else 711 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 712 #endif 713 714 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 715