1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * Copyright 2009-2010 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * 4a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 5a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 6a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 7a47a12beSStefan Roese * the License, or (at your option) any later version. 8a47a12beSStefan Roese * 9a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 10a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 11a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12a47a12beSStefan Roese * GNU General Public License for more details. 13a47a12beSStefan Roese * 14a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 15a47a12beSStefan Roese * along with this program; if not, write to the Free Software 16a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17a47a12beSStefan Roese * MA 02111-1307 USA 18a47a12beSStefan Roese * 19a47a12beSStefan Roese */ 20a47a12beSStefan Roese 21a47a12beSStefan Roese #ifndef _ASM_CONFIG_H_ 22a47a12beSStefan Roese #define _ASM_CONFIG_H_ 23a47a12beSStefan Roese 24a47a12beSStefan Roese #define CONFIG_LMB 25a47a12beSStefan Roese 26a47a12beSStefan Roese #ifndef CONFIG_MAX_MEM_MAPPED 27a47a12beSStefan Roese #if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 28a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 29a47a12beSStefan Roese #else 30a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED (256 << 20) 31a47a12beSStefan Roese #endif 32a47a12beSStefan Roese #endif 33a47a12beSStefan Roese 34a47a12beSStefan Roese /* Check if boards need to enable FSL DMA engine for SDRAM init */ 35a47a12beSStefan Roese #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 36a47a12beSStefan Roese #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 37a47a12beSStefan Roese ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 38a47a12beSStefan Roese !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 39a47a12beSStefan Roese #define CONFIG_FSL_DMA 40a47a12beSStefan Roese #endif 41a47a12beSStefan Roese #endif 42a47a12beSStefan Roese 43a47a12beSStefan Roese #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ 44a47a12beSStefan Roese defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ 45a47a12beSStefan Roese defined(CONFIG_P2020) || defined(CONFIG_MPC8641) 46a47a12beSStefan Roese #define CONFIG_MAX_CPUS 2 47c26de2d8SKumar Gala #elif defined(CONFIG_PPC_P3041) 48c26de2d8SKumar Gala #define CONFIG_MAX_CPUS 4 49a47a12beSStefan Roese #elif defined(CONFIG_PPC_P4080) 50a47a12beSStefan Roese #define CONFIG_MAX_CPUS 8 5119dbcc96SKumar Gala #elif defined(CONFIG_PPC_P5020) 5219dbcc96SKumar Gala #define CONFIG_MAX_CPUS 2 53a47a12beSStefan Roese #else 54a47a12beSStefan Roese #define CONFIG_MAX_CPUS 1 55a47a12beSStefan Roese #endif 56a47a12beSStefan Roese 57a47a12beSStefan Roese /* 58a47a12beSStefan Roese * Provide a default boot page translation virtual address that lines up with 59a47a12beSStefan Roese * Freescale's default e500 reset page. 60a47a12beSStefan Roese */ 61a47a12beSStefan Roese #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 62a47a12beSStefan Roese #ifndef CONFIG_BPTR_VIRT_ADDR 63a47a12beSStefan Roese #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 64a47a12beSStefan Roese #endif 65a47a12beSStefan Roese #endif 66a47a12beSStefan Roese 67a47a12beSStefan Roese /* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ 68a47a12beSStefan Roese #if defined(CONFIG_TSEC_ENET) && \ 69a47a12beSStefan Roese (defined(CONFIG_P1020) || defined(CONFIG_P1011)) 70a47a12beSStefan Roese #define CONFIG_TSECV2 71a47a12beSStefan Roese #endif 72a47a12beSStefan Roese 73929a2138SKim Phillips /* 74929a2138SKim Phillips * SEC (crypto unit) major compatible version determination 75929a2138SKim Phillips */ 7622f292c7SKim Phillips #if defined(CONFIG_FSL_CORENET) 7722f292c7SKim Phillips #define CONFIG_SYS_FSL_SEC_COMPAT 4 7822f292c7SKim Phillips #elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx) 79929a2138SKim Phillips #define CONFIG_SYS_FSL_SEC_COMPAT 2 80929a2138SKim Phillips #endif 81929a2138SKim Phillips 82a47a12beSStefan Roese /* Number of TLB CAM entries we have on FSL Book-E chips */ 83a47a12beSStefan Roese #if defined(CONFIG_E500MC) 84a47a12beSStefan Roese #define CONFIG_SYS_NUM_TLBCAMS 64 85a47a12beSStefan Roese #elif defined(CONFIG_E500) 86a47a12beSStefan Roese #define CONFIG_SYS_NUM_TLBCAMS 16 87a47a12beSStefan Roese #endif 88a47a12beSStefan Roese 89a47a12beSStefan Roese /* Relocation to SDRAM works on all PPC boards */ 90a47a12beSStefan Roese #define CONFIG_RELOC_FIXUP_WORKS 91a47a12beSStefan Roese 92f51cdaf1SBecky Bruce /* Since so many PPC SOCs have a semi-common LBC, define this here */ 93f51cdaf1SBecky Bruce #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 94f51cdaf1SBecky Bruce defined(CONFIG_MPC83xx) 95f51cdaf1SBecky Bruce #define CONFIG_FSL_LBC 96f51cdaf1SBecky Bruce #endif 97f51cdaf1SBecky Bruce 98*f2a37fcdSAlbert Aribaud /* All PPC boards must swap IDE bytes */ 99*f2a37fcdSAlbert Aribaud #define CONFIG_IDE_SWAP_IO 100*f2a37fcdSAlbert Aribaud 101a47a12beSStefan Roese #endif /* _ASM_CONFIG_H_ */ 102