1a47a12beSStefan Roese /* 2b8cdd014SPoonam Aggrwal * Copyright 2009-2011 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5a47a12beSStefan Roese */ 6a47a12beSStefan Roese 7a47a12beSStefan Roese #ifndef _ASM_CONFIG_H_ 8a47a12beSStefan Roese #define _ASM_CONFIG_H_ 9a47a12beSStefan Roese 10243be8e2SKumar Gala #ifdef CONFIG_MPC85xx 11243be8e2SKumar Gala #include <asm/config_mpc85xx.h> 125614e71bSYork Sun #define CONFIG_SYS_FSL_DDR 13243be8e2SKumar Gala #endif 14243be8e2SKumar Gala 15243be8e2SKumar Gala #ifdef CONFIG_MPC86xx 16243be8e2SKumar Gala #include <asm/config_mpc86xx.h> 175614e71bSYork Sun #define CONFIG_SYS_FSL_DDR 185614e71bSYork Sun #endif 195614e71bSYork Sun 205614e71bSYork Sun #ifdef CONFIG_MPC83xx 215614e71bSYork Sun #define CONFIG_SYS_FSL_DDR 22243be8e2SKumar Gala #endif 23243be8e2SKumar Gala 247ac3cc20SYork Sun #ifndef HWCONFIG_BUFFER_SIZE 257ac3cc20SYork Sun #define HWCONFIG_BUFFER_SIZE 256 267ac3cc20SYork Sun #endif 277ac3cc20SYork Sun 28273feafeSMingkai Hu /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ 29273feafeSMingkai Hu #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) 30273feafeSMingkai Hu # ifndef CONFIG_HARD_SPI 31273feafeSMingkai Hu # define CONFIG_HARD_SPI 32273feafeSMingkai Hu # endif 33273feafeSMingkai Hu #endif 34273feafeSMingkai Hu 35a47a12beSStefan Roese #define CONFIG_LMB 36fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_RAMDISK_HIGH 37fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_GET_CMDLINE 38fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_GET_KBD 39a47a12beSStefan Roese 40a47a12beSStefan Roese #ifndef CONFIG_MAX_MEM_MAPPED 41d29d17d7SYork Sun #if defined(CONFIG_4xx) || \ 42d29d17d7SYork Sun defined(CONFIG_E500) || \ 43d29d17d7SYork Sun defined(CONFIG_MPC86xx) || \ 44d29d17d7SYork Sun defined(CONFIG_E300) 45a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 46a47a12beSStefan Roese #else 47a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED (256 << 20) 48a47a12beSStefan Roese #endif 49a47a12beSStefan Roese #endif 50a47a12beSStefan Roese 51a47a12beSStefan Roese /* Check if boards need to enable FSL DMA engine for SDRAM init */ 52a47a12beSStefan Roese #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 53a47a12beSStefan Roese #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 54a47a12beSStefan Roese ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 55a47a12beSStefan Roese !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 56a47a12beSStefan Roese #define CONFIG_FSL_DMA 57a47a12beSStefan Roese #endif 58a47a12beSStefan Roese #endif 59a47a12beSStefan Roese 60243be8e2SKumar Gala #ifndef CONFIG_MAX_CPUS 61a47a12beSStefan Roese #define CONFIG_MAX_CPUS 1 62a47a12beSStefan Roese #endif 63a47a12beSStefan Roese 64a47a12beSStefan Roese /* 65a47a12beSStefan Roese * Provide a default boot page translation virtual address that lines up with 66a47a12beSStefan Roese * Freescale's default e500 reset page. 67a47a12beSStefan Roese */ 68a47a12beSStefan Roese #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 69a47a12beSStefan Roese #ifndef CONFIG_BPTR_VIRT_ADDR 70a47a12beSStefan Roese #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 71a47a12beSStefan Roese #endif 72a47a12beSStefan Roese #endif 73a47a12beSStefan Roese 74929a2138SKim Phillips /* 75929a2138SKim Phillips * SEC (crypto unit) major compatible version determination 76929a2138SKim Phillips */ 77243be8e2SKumar Gala #if defined(CONFIG_MPC83xx) 780181937fSRuchika Gupta #define CONFIG_SYS_FSL_SEC_BE 79929a2138SKim Phillips #define CONFIG_SYS_FSL_SEC_COMPAT 2 80929a2138SKim Phillips #endif 81929a2138SKim Phillips 82f51cdaf1SBecky Bruce /* Since so many PPC SOCs have a semi-common LBC, define this here */ 83f51cdaf1SBecky Bruce #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 84f51cdaf1SBecky Bruce defined(CONFIG_MPC83xx) 85d789b5f5SDipen Dudhat #if !defined(CONFIG_FSL_IFC) 86f51cdaf1SBecky Bruce #define CONFIG_FSL_LBC 87f51cdaf1SBecky Bruce #endif 88d789b5f5SDipen Dudhat #endif 89f51cdaf1SBecky Bruce 90063c1263SAndy Fleming /* The TSEC driver uses the PHYLIB infrastructure */ 91063c1263SAndy Fleming #ifndef CONFIG_PHYLIB 92063c1263SAndy Fleming #if defined(CONFIG_TSEC_ENET) 93063c1263SAndy Fleming #define CONFIG_PHYLIB 94063c1263SAndy Fleming 95063c1263SAndy Fleming #include <config_phylib_all_drivers.h> 96063c1263SAndy Fleming #endif /* TSEC_ENET */ 97063c1263SAndy Fleming #endif /* !CONFIG_PHYLIB */ 98063c1263SAndy Fleming 99c916d7c9SKumar Gala /* The FMAN driver uses the PHYLIB infrastructure */ 100c916d7c9SKumar Gala #if defined(CONFIG_FMAN_ENET) 101c916d7c9SKumar Gala #define CONFIG_PHYLIB 102c916d7c9SKumar Gala #endif 103c916d7c9SKumar Gala 104f2a37fcdSAlbert Aribaud /* All PPC boards must swap IDE bytes */ 105f2a37fcdSAlbert Aribaud #define CONFIG_IDE_SWAP_IO 106f2a37fcdSAlbert Aribaud 107*f27445cbSThomas Chou #if defined(CONFIG_DM_SERIAL) 108*f27445cbSThomas Chou /* 109*f27445cbSThomas Chou * TODO: Convert this to a clock driver exists that can give us the UART 110*f27445cbSThomas Chou * clock here. 111*f27445cbSThomas Chou */ 112*f27445cbSThomas Chou #define CONFIG_SYS_NS16550_CLK get_serial_clock() 113*f27445cbSThomas Chou #endif 114*f27445cbSThomas Chou 115a47a12beSStefan Roese #endif /* _ASM_CONFIG_H_ */ 116