1a47a12beSStefan Roese /* 2b8cdd014SPoonam Aggrwal * Copyright 2009-2011 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * 4a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 5a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 6a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 7a47a12beSStefan Roese * the License, or (at your option) any later version. 8a47a12beSStefan Roese * 9a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 10a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 11a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12a47a12beSStefan Roese * GNU General Public License for more details. 13a47a12beSStefan Roese * 14a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 15a47a12beSStefan Roese * along with this program; if not, write to the Free Software 16a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17a47a12beSStefan Roese * MA 02111-1307 USA 18a47a12beSStefan Roese * 19a47a12beSStefan Roese */ 20a47a12beSStefan Roese 21a47a12beSStefan Roese #ifndef _ASM_CONFIG_H_ 22a47a12beSStefan Roese #define _ASM_CONFIG_H_ 23a47a12beSStefan Roese 24243be8e2SKumar Gala #ifdef CONFIG_MPC85xx 25243be8e2SKumar Gala #include <asm/config_mpc85xx.h> 26243be8e2SKumar Gala #endif 27243be8e2SKumar Gala 28243be8e2SKumar Gala #ifdef CONFIG_MPC86xx 29243be8e2SKumar Gala #include <asm/config_mpc86xx.h> 30243be8e2SKumar Gala #endif 31243be8e2SKumar Gala 32273feafeSMingkai Hu /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ 33273feafeSMingkai Hu #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) 34273feafeSMingkai Hu # ifndef CONFIG_HARD_SPI 35273feafeSMingkai Hu # define CONFIG_HARD_SPI 36273feafeSMingkai Hu # endif 37273feafeSMingkai Hu #endif 38273feafeSMingkai Hu 39a47a12beSStefan Roese #define CONFIG_LMB 40fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_RAMDISK_HIGH 41fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_GET_CMDLINE 42fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_GET_KBD 43a47a12beSStefan Roese 44a47a12beSStefan Roese #ifndef CONFIG_MAX_MEM_MAPPED 45*d29d17d7SYork Sun #if defined(CONFIG_4xx) || \ 46*d29d17d7SYork Sun defined(CONFIG_E500) || \ 47*d29d17d7SYork Sun defined(CONFIG_MPC86xx) || \ 48*d29d17d7SYork Sun defined(CONFIG_E300) 49a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 50a47a12beSStefan Roese #else 51a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED (256 << 20) 52a47a12beSStefan Roese #endif 53a47a12beSStefan Roese #endif 54a47a12beSStefan Roese 55a47a12beSStefan Roese /* Check if boards need to enable FSL DMA engine for SDRAM init */ 56a47a12beSStefan Roese #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 57a47a12beSStefan Roese #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 58a47a12beSStefan Roese ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 59a47a12beSStefan Roese !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 60a47a12beSStefan Roese #define CONFIG_FSL_DMA 61a47a12beSStefan Roese #endif 62a47a12beSStefan Roese #endif 63a47a12beSStefan Roese 64243be8e2SKumar Gala #ifndef CONFIG_MAX_CPUS 65a47a12beSStefan Roese #define CONFIG_MAX_CPUS 1 66a47a12beSStefan Roese #endif 67a47a12beSStefan Roese 68a47a12beSStefan Roese /* 69a47a12beSStefan Roese * Provide a default boot page translation virtual address that lines up with 70a47a12beSStefan Roese * Freescale's default e500 reset page. 71a47a12beSStefan Roese */ 72a47a12beSStefan Roese #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 73a47a12beSStefan Roese #ifndef CONFIG_BPTR_VIRT_ADDR 74a47a12beSStefan Roese #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 75a47a12beSStefan Roese #endif 76a47a12beSStefan Roese #endif 77a47a12beSStefan Roese 78929a2138SKim Phillips /* 79929a2138SKim Phillips * SEC (crypto unit) major compatible version determination 80929a2138SKim Phillips */ 81243be8e2SKumar Gala #if defined(CONFIG_MPC83xx) 82929a2138SKim Phillips #define CONFIG_SYS_FSL_SEC_COMPAT 2 83929a2138SKim Phillips #endif 84929a2138SKim Phillips 85f51cdaf1SBecky Bruce /* Since so many PPC SOCs have a semi-common LBC, define this here */ 86f51cdaf1SBecky Bruce #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 87f51cdaf1SBecky Bruce defined(CONFIG_MPC83xx) 88d789b5f5SDipen Dudhat #if !defined(CONFIG_FSL_IFC) 89f51cdaf1SBecky Bruce #define CONFIG_FSL_LBC 90f51cdaf1SBecky Bruce #endif 91d789b5f5SDipen Dudhat #endif 92f51cdaf1SBecky Bruce 93063c1263SAndy Fleming /* The TSEC driver uses the PHYLIB infrastructure */ 94063c1263SAndy Fleming #ifndef CONFIG_PHYLIB 95063c1263SAndy Fleming #if defined(CONFIG_TSEC_ENET) 96063c1263SAndy Fleming #define CONFIG_PHYLIB 97063c1263SAndy Fleming 98063c1263SAndy Fleming #include <config_phylib_all_drivers.h> 99063c1263SAndy Fleming #endif /* TSEC_ENET */ 100063c1263SAndy Fleming #endif /* !CONFIG_PHYLIB */ 101063c1263SAndy Fleming 102c916d7c9SKumar Gala /* The FMAN driver uses the PHYLIB infrastructure */ 103c916d7c9SKumar Gala #if defined(CONFIG_FMAN_ENET) 104c916d7c9SKumar Gala #define CONFIG_PHYLIB 105c916d7c9SKumar Gala #endif 106c916d7c9SKumar Gala 107f2a37fcdSAlbert Aribaud /* All PPC boards must swap IDE bytes */ 108f2a37fcdSAlbert Aribaud #define CONFIG_IDE_SWAP_IO 109f2a37fcdSAlbert Aribaud 110a47a12beSStefan Roese #endif /* _ASM_CONFIG_H_ */ 111