1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * Copyright 2009-2010 Freescale Semiconductor, Inc. 3*a47a12beSStefan Roese * 4*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 5*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 6*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 7*a47a12beSStefan Roese * the License, or (at your option) any later version. 8*a47a12beSStefan Roese * 9*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 10*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*a47a12beSStefan Roese * GNU General Public License for more details. 13*a47a12beSStefan Roese * 14*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 15*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 16*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17*a47a12beSStefan Roese * MA 02111-1307 USA 18*a47a12beSStefan Roese * 19*a47a12beSStefan Roese */ 20*a47a12beSStefan Roese 21*a47a12beSStefan Roese #ifndef _ASM_CONFIG_H_ 22*a47a12beSStefan Roese #define _ASM_CONFIG_H_ 23*a47a12beSStefan Roese 24*a47a12beSStefan Roese #define CONFIG_LMB 25*a47a12beSStefan Roese 26*a47a12beSStefan Roese #ifndef CONFIG_MAX_MEM_MAPPED 27*a47a12beSStefan Roese #if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 28*a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 29*a47a12beSStefan Roese #else 30*a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED (256 << 20) 31*a47a12beSStefan Roese #endif 32*a47a12beSStefan Roese #endif 33*a47a12beSStefan Roese 34*a47a12beSStefan Roese /* Check if boards need to enable FSL DMA engine for SDRAM init */ 35*a47a12beSStefan Roese #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 36*a47a12beSStefan Roese #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 37*a47a12beSStefan Roese ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 38*a47a12beSStefan Roese !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 39*a47a12beSStefan Roese #define CONFIG_FSL_DMA 40*a47a12beSStefan Roese #endif 41*a47a12beSStefan Roese #endif 42*a47a12beSStefan Roese 43*a47a12beSStefan Roese #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ 44*a47a12beSStefan Roese defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ 45*a47a12beSStefan Roese defined(CONFIG_P2020) || defined(CONFIG_MPC8641) 46*a47a12beSStefan Roese #define CONFIG_MAX_CPUS 2 47*a47a12beSStefan Roese #elif defined(CONFIG_PPC_P4080) 48*a47a12beSStefan Roese #define CONFIG_MAX_CPUS 8 49*a47a12beSStefan Roese #else 50*a47a12beSStefan Roese #define CONFIG_MAX_CPUS 1 51*a47a12beSStefan Roese #endif 52*a47a12beSStefan Roese 53*a47a12beSStefan Roese /* 54*a47a12beSStefan Roese * Provide a default boot page translation virtual address that lines up with 55*a47a12beSStefan Roese * Freescale's default e500 reset page. 56*a47a12beSStefan Roese */ 57*a47a12beSStefan Roese #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 58*a47a12beSStefan Roese #ifndef CONFIG_BPTR_VIRT_ADDR 59*a47a12beSStefan Roese #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 60*a47a12beSStefan Roese #endif 61*a47a12beSStefan Roese #endif 62*a47a12beSStefan Roese 63*a47a12beSStefan Roese /* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ 64*a47a12beSStefan Roese #if defined(CONFIG_TSEC_ENET) && \ 65*a47a12beSStefan Roese (defined(CONFIG_P1020) || defined(CONFIG_P1011)) 66*a47a12beSStefan Roese #define CONFIG_TSECV2 67*a47a12beSStefan Roese #endif 68*a47a12beSStefan Roese 69*a47a12beSStefan Roese /* Number of TLB CAM entries we have on FSL Book-E chips */ 70*a47a12beSStefan Roese #if defined(CONFIG_E500MC) 71*a47a12beSStefan Roese #define CONFIG_SYS_NUM_TLBCAMS 64 72*a47a12beSStefan Roese #elif defined(CONFIG_E500) 73*a47a12beSStefan Roese #define CONFIG_SYS_NUM_TLBCAMS 16 74*a47a12beSStefan Roese #endif 75*a47a12beSStefan Roese 76*a47a12beSStefan Roese /* Relocation to SDRAM works on all PPC boards */ 77*a47a12beSStefan Roese #define CONFIG_RELOC_FIXUP_WORKS 78*a47a12beSStefan Roese 79*a47a12beSStefan Roese #endif /* _ASM_CONFIG_H_ */ 80