1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2a47a12beSStefan Roese /* 3b8cdd014SPoonam Aggrwal * Copyright 2009-2011 Freescale Semiconductor, Inc. 4a47a12beSStefan Roese */ 5a47a12beSStefan Roese 6a47a12beSStefan Roese #ifndef _ASM_CONFIG_H_ 7a47a12beSStefan Roese #define _ASM_CONFIG_H_ 8a47a12beSStefan Roese 9243be8e2SKumar Gala #ifdef CONFIG_MPC85xx 10243be8e2SKumar Gala #include <asm/config_mpc85xx.h> 11243be8e2SKumar Gala #endif 12243be8e2SKumar Gala 13243be8e2SKumar Gala #ifdef CONFIG_MPC86xx 14243be8e2SKumar Gala #include <asm/config_mpc86xx.h> 155614e71bSYork Sun #endif 165614e71bSYork Sun 175614e71bSYork Sun #ifdef CONFIG_MPC83xx 18243be8e2SKumar Gala #endif 19243be8e2SKumar Gala 207ac3cc20SYork Sun #ifndef HWCONFIG_BUFFER_SIZE 217ac3cc20SYork Sun #define HWCONFIG_BUFFER_SIZE 256 227ac3cc20SYork Sun #endif 237ac3cc20SYork Sun 24273feafeSMingkai Hu /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ 25273feafeSMingkai Hu #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) 26273feafeSMingkai Hu # ifndef CONFIG_HARD_SPI 27273feafeSMingkai Hu # define CONFIG_HARD_SPI 28273feafeSMingkai Hu # endif 29273feafeSMingkai Hu #endif 30273feafeSMingkai Hu 31a47a12beSStefan Roese #define CONFIG_LMB 32fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_RAMDISK_HIGH 33a47a12beSStefan Roese 34a47a12beSStefan Roese #ifndef CONFIG_MAX_MEM_MAPPED 3598f705c9SHeiko Schocher #if defined(CONFIG_E500) || \ 36d29d17d7SYork Sun defined(CONFIG_MPC86xx) || \ 37d29d17d7SYork Sun defined(CONFIG_E300) 38a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 39a47a12beSStefan Roese #else 40a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED (256 << 20) 41a47a12beSStefan Roese #endif 42a47a12beSStefan Roese #endif 43a47a12beSStefan Roese 44a47a12beSStefan Roese /* Check if boards need to enable FSL DMA engine for SDRAM init */ 45a47a12beSStefan Roese #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 46a47a12beSStefan Roese #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 47a47a12beSStefan Roese ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 48a47a12beSStefan Roese !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 49a47a12beSStefan Roese #define CONFIG_FSL_DMA 50a47a12beSStefan Roese #endif 51a47a12beSStefan Roese #endif 52a47a12beSStefan Roese 53a47a12beSStefan Roese /* 54a47a12beSStefan Roese * Provide a default boot page translation virtual address that lines up with 55a47a12beSStefan Roese * Freescale's default e500 reset page. 56a47a12beSStefan Roese */ 57a47a12beSStefan Roese #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 58a47a12beSStefan Roese #ifndef CONFIG_BPTR_VIRT_ADDR 59a47a12beSStefan Roese #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 60a47a12beSStefan Roese #endif 61a47a12beSStefan Roese #endif 62a47a12beSStefan Roese 63f51cdaf1SBecky Bruce /* Since so many PPC SOCs have a semi-common LBC, define this here */ 64f51cdaf1SBecky Bruce #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 65f51cdaf1SBecky Bruce defined(CONFIG_MPC83xx) 66d789b5f5SDipen Dudhat #if !defined(CONFIG_FSL_IFC) 67f51cdaf1SBecky Bruce #define CONFIG_FSL_LBC 68f51cdaf1SBecky Bruce #endif 69d789b5f5SDipen Dudhat #endif 70f51cdaf1SBecky Bruce 71063c1263SAndy Fleming /* The TSEC driver uses the PHYLIB infrastructure */ 72990d06b0SZhao Qiang #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB) 73063c1263SAndy Fleming #include <config_phylib_all_drivers.h> 74063c1263SAndy Fleming #endif /* TSEC_ENET */ 75063c1263SAndy Fleming 76c916d7c9SKumar Gala /* The FMAN driver uses the PHYLIB infrastructure */ 77c916d7c9SKumar Gala 78f2a37fcdSAlbert Aribaud /* All PPC boards must swap IDE bytes */ 79f2a37fcdSAlbert Aribaud #define CONFIG_IDE_SWAP_IO 80f2a37fcdSAlbert Aribaud 81f27445cbSThomas Chou #if defined(CONFIG_DM_SERIAL) 82f27445cbSThomas Chou /* 83f27445cbSThomas Chou * TODO: Convert this to a clock driver exists that can give us the UART 84f27445cbSThomas Chou * clock here. 85f27445cbSThomas Chou */ 86f27445cbSThomas Chou #define CONFIG_SYS_NS16550_CLK get_serial_clock() 87f27445cbSThomas Chou #endif 88f27445cbSThomas Chou 89a47a12beSStefan Roese #endif /* _ASM_CONFIG_H_ */ 90