1a47a12beSStefan Roese /* 2b8cdd014SPoonam Aggrwal * Copyright 2009-2011 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5a47a12beSStefan Roese */ 6a47a12beSStefan Roese 7a47a12beSStefan Roese #ifndef _ASM_CONFIG_H_ 8a47a12beSStefan Roese #define _ASM_CONFIG_H_ 9a47a12beSStefan Roese 10243be8e2SKumar Gala #ifdef CONFIG_MPC85xx 11243be8e2SKumar Gala #include <asm/config_mpc85xx.h> 12243be8e2SKumar Gala #endif 13243be8e2SKumar Gala 14243be8e2SKumar Gala #ifdef CONFIG_MPC86xx 15243be8e2SKumar Gala #include <asm/config_mpc86xx.h> 16243be8e2SKumar Gala #endif 17243be8e2SKumar Gala 187ac3cc20SYork Sun #ifndef HWCONFIG_BUFFER_SIZE 197ac3cc20SYork Sun #define HWCONFIG_BUFFER_SIZE 256 207ac3cc20SYork Sun #endif 217ac3cc20SYork Sun 22273feafeSMingkai Hu /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ 23273feafeSMingkai Hu #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) 24273feafeSMingkai Hu # ifndef CONFIG_HARD_SPI 25273feafeSMingkai Hu # define CONFIG_HARD_SPI 26273feafeSMingkai Hu # endif 27273feafeSMingkai Hu #endif 28273feafeSMingkai Hu 29a47a12beSStefan Roese #define CONFIG_LMB 30fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_RAMDISK_HIGH 31fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_GET_CMDLINE 32fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_GET_KBD 33a47a12beSStefan Roese 34a47a12beSStefan Roese #ifndef CONFIG_MAX_MEM_MAPPED 35d29d17d7SYork Sun #if defined(CONFIG_4xx) || \ 36d29d17d7SYork Sun defined(CONFIG_E500) || \ 37d29d17d7SYork Sun defined(CONFIG_MPC86xx) || \ 38d29d17d7SYork Sun defined(CONFIG_E300) 39a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 40a47a12beSStefan Roese #else 41a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED (256 << 20) 42a47a12beSStefan Roese #endif 43a47a12beSStefan Roese #endif 44a47a12beSStefan Roese 45a47a12beSStefan Roese /* Check if boards need to enable FSL DMA engine for SDRAM init */ 46a47a12beSStefan Roese #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 47a47a12beSStefan Roese #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 48a47a12beSStefan Roese ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 49a47a12beSStefan Roese !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 50a47a12beSStefan Roese #define CONFIG_FSL_DMA 51a47a12beSStefan Roese #endif 52a47a12beSStefan Roese #endif 53a47a12beSStefan Roese 54243be8e2SKumar Gala #ifndef CONFIG_MAX_CPUS 55a47a12beSStefan Roese #define CONFIG_MAX_CPUS 1 56a47a12beSStefan Roese #endif 57a47a12beSStefan Roese 58a47a12beSStefan Roese /* 59a47a12beSStefan Roese * Provide a default boot page translation virtual address that lines up with 60a47a12beSStefan Roese * Freescale's default e500 reset page. 61a47a12beSStefan Roese */ 62a47a12beSStefan Roese #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 63a47a12beSStefan Roese #ifndef CONFIG_BPTR_VIRT_ADDR 64a47a12beSStefan Roese #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 65a47a12beSStefan Roese #endif 66a47a12beSStefan Roese #endif 67a47a12beSStefan Roese 68929a2138SKim Phillips /* 69929a2138SKim Phillips * SEC (crypto unit) major compatible version determination 70929a2138SKim Phillips */ 71243be8e2SKumar Gala #if defined(CONFIG_MPC83xx) 72929a2138SKim Phillips #define CONFIG_SYS_FSL_SEC_COMPAT 2 73929a2138SKim Phillips #endif 74929a2138SKim Phillips 75f51cdaf1SBecky Bruce /* Since so many PPC SOCs have a semi-common LBC, define this here */ 76f51cdaf1SBecky Bruce #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 77f51cdaf1SBecky Bruce defined(CONFIG_MPC83xx) 78d789b5f5SDipen Dudhat #if !defined(CONFIG_FSL_IFC) 79f51cdaf1SBecky Bruce #define CONFIG_FSL_LBC 80f51cdaf1SBecky Bruce #endif 81d789b5f5SDipen Dudhat #endif 82f51cdaf1SBecky Bruce 83063c1263SAndy Fleming /* The TSEC driver uses the PHYLIB infrastructure */ 84063c1263SAndy Fleming #ifndef CONFIG_PHYLIB 85063c1263SAndy Fleming #if defined(CONFIG_TSEC_ENET) 86063c1263SAndy Fleming #define CONFIG_PHYLIB 87063c1263SAndy Fleming 88063c1263SAndy Fleming #include <config_phylib_all_drivers.h> 89063c1263SAndy Fleming #endif /* TSEC_ENET */ 90063c1263SAndy Fleming #endif /* !CONFIG_PHYLIB */ 91063c1263SAndy Fleming 92c916d7c9SKumar Gala /* The FMAN driver uses the PHYLIB infrastructure */ 93c916d7c9SKumar Gala #if defined(CONFIG_FMAN_ENET) 94c916d7c9SKumar Gala #define CONFIG_PHYLIB 95c916d7c9SKumar Gala #endif 96c916d7c9SKumar Gala 97f2a37fcdSAlbert Aribaud /* All PPC boards must swap IDE bytes */ 98f2a37fcdSAlbert Aribaud #define CONFIG_IDE_SWAP_IO 99f2a37fcdSAlbert Aribaud 100a47a12beSStefan Roese #endif /* _ASM_CONFIG_H_ */ 101