1a47a12beSStefan Roese /* 2b8cdd014SPoonam Aggrwal * Copyright 2009-2011 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * 4a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 5a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 6a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 7a47a12beSStefan Roese * the License, or (at your option) any later version. 8a47a12beSStefan Roese * 9a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 10a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 11a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12a47a12beSStefan Roese * GNU General Public License for more details. 13a47a12beSStefan Roese * 14a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 15a47a12beSStefan Roese * along with this program; if not, write to the Free Software 16a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17a47a12beSStefan Roese * MA 02111-1307 USA 18a47a12beSStefan Roese * 19a47a12beSStefan Roese */ 20a47a12beSStefan Roese 21a47a12beSStefan Roese #ifndef _ASM_CONFIG_H_ 22a47a12beSStefan Roese #define _ASM_CONFIG_H_ 23a47a12beSStefan Roese 24243be8e2SKumar Gala #ifdef CONFIG_MPC85xx 25243be8e2SKumar Gala #include <asm/config_mpc85xx.h> 26243be8e2SKumar Gala #endif 27243be8e2SKumar Gala 28243be8e2SKumar Gala #ifdef CONFIG_MPC86xx 29243be8e2SKumar Gala #include <asm/config_mpc86xx.h> 30243be8e2SKumar Gala #endif 31243be8e2SKumar Gala 32a47a12beSStefan Roese #define CONFIG_LMB 33fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_RAMDISK_HIGH 34fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_GET_CMDLINE 35fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_GET_KBD 36a47a12beSStefan Roese 37a47a12beSStefan Roese #ifndef CONFIG_MAX_MEM_MAPPED 38a47a12beSStefan Roese #if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 39a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 40a47a12beSStefan Roese #else 41a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED (256 << 20) 42a47a12beSStefan Roese #endif 43a47a12beSStefan Roese #endif 44a47a12beSStefan Roese 45a47a12beSStefan Roese /* Check if boards need to enable FSL DMA engine for SDRAM init */ 46a47a12beSStefan Roese #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 47a47a12beSStefan Roese #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 48a47a12beSStefan Roese ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 49a47a12beSStefan Roese !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 50a47a12beSStefan Roese #define CONFIG_FSL_DMA 51a47a12beSStefan Roese #endif 52a47a12beSStefan Roese #endif 53a47a12beSStefan Roese 54243be8e2SKumar Gala #ifndef CONFIG_MAX_CPUS 55a47a12beSStefan Roese #define CONFIG_MAX_CPUS 1 56a47a12beSStefan Roese #endif 57a47a12beSStefan Roese 58a47a12beSStefan Roese /* 59a47a12beSStefan Roese * Provide a default boot page translation virtual address that lines up with 60a47a12beSStefan Roese * Freescale's default e500 reset page. 61a47a12beSStefan Roese */ 62a47a12beSStefan Roese #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 63a47a12beSStefan Roese #ifndef CONFIG_BPTR_VIRT_ADDR 64a47a12beSStefan Roese #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 65a47a12beSStefan Roese #endif 66a47a12beSStefan Roese #endif 67a47a12beSStefan Roese 68929a2138SKim Phillips /* 69929a2138SKim Phillips * SEC (crypto unit) major compatible version determination 70929a2138SKim Phillips */ 71243be8e2SKumar Gala #if defined(CONFIG_MPC83xx) 72929a2138SKim Phillips #define CONFIG_SYS_FSL_SEC_COMPAT 2 73929a2138SKim Phillips #endif 74929a2138SKim Phillips 75f51cdaf1SBecky Bruce /* Since so many PPC SOCs have a semi-common LBC, define this here */ 76f51cdaf1SBecky Bruce #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 77f51cdaf1SBecky Bruce defined(CONFIG_MPC83xx) 78d789b5f5SDipen Dudhat #if !defined(CONFIG_FSL_IFC) 79f51cdaf1SBecky Bruce #define CONFIG_FSL_LBC 80f51cdaf1SBecky Bruce #endif 81d789b5f5SDipen Dudhat #endif 82f51cdaf1SBecky Bruce 83*063c1263SAndy Fleming /* The TSEC driver uses the PHYLIB infrastructure */ 84*063c1263SAndy Fleming #ifndef CONFIG_PHYLIB 85*063c1263SAndy Fleming #if defined(CONFIG_TSEC_ENET) 86*063c1263SAndy Fleming #define CONFIG_PHYLIB 87*063c1263SAndy Fleming 88*063c1263SAndy Fleming #include <config_phylib_all_drivers.h> 89*063c1263SAndy Fleming #endif /* TSEC_ENET */ 90*063c1263SAndy Fleming #endif /* !CONFIG_PHYLIB */ 91*063c1263SAndy Fleming 92f2a37fcdSAlbert Aribaud /* All PPC boards must swap IDE bytes */ 93f2a37fcdSAlbert Aribaud #define CONFIG_IDE_SWAP_IO 94f2a37fcdSAlbert Aribaud 95a47a12beSStefan Roese #endif /* _ASM_CONFIG_H_ */ 96