183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2a47a12beSStefan Roese /* 3b8cdd014SPoonam Aggrwal * Copyright 2009-2011 Freescale Semiconductor, Inc. 4a47a12beSStefan Roese */ 5a47a12beSStefan Roese 6a47a12beSStefan Roese #ifndef _ASM_CONFIG_H_ 7a47a12beSStefan Roese #define _ASM_CONFIG_H_ 8a47a12beSStefan Roese 9243be8e2SKumar Gala #ifdef CONFIG_MPC85xx 10243be8e2SKumar Gala #include <asm/config_mpc85xx.h> 11243be8e2SKumar Gala #endif 12243be8e2SKumar Gala 13243be8e2SKumar Gala #ifdef CONFIG_MPC86xx 14243be8e2SKumar Gala #include <asm/config_mpc86xx.h> 155614e71bSYork Sun #endif 165614e71bSYork Sun 177ac3cc20SYork Sun #ifndef HWCONFIG_BUFFER_SIZE 187ac3cc20SYork Sun #define HWCONFIG_BUFFER_SIZE 256 197ac3cc20SYork Sun #endif 207ac3cc20SYork Sun 21a47a12beSStefan Roese #define CONFIG_LMB 22fca43cc8SJohn Rigby #define CONFIG_SYS_BOOT_RAMDISK_HIGH 23a47a12beSStefan Roese 24a47a12beSStefan Roese #ifndef CONFIG_MAX_MEM_MAPPED 2598f705c9SHeiko Schocher #if defined(CONFIG_E500) || \ 26d29d17d7SYork Sun defined(CONFIG_MPC86xx) || \ 27d29d17d7SYork Sun defined(CONFIG_E300) 28a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 29a47a12beSStefan Roese #else 30a47a12beSStefan Roese #define CONFIG_MAX_MEM_MAPPED (256 << 20) 31a47a12beSStefan Roese #endif 32a47a12beSStefan Roese #endif 33a47a12beSStefan Roese 34a47a12beSStefan Roese /* Check if boards need to enable FSL DMA engine for SDRAM init */ 35a47a12beSStefan Roese #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 36a47a12beSStefan Roese #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 37a47a12beSStefan Roese ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 38a47a12beSStefan Roese !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 39a47a12beSStefan Roese #define CONFIG_FSL_DMA 40a47a12beSStefan Roese #endif 41a47a12beSStefan Roese #endif 42a47a12beSStefan Roese 43a47a12beSStefan Roese /* 44a47a12beSStefan Roese * Provide a default boot page translation virtual address that lines up with 45a47a12beSStefan Roese * Freescale's default e500 reset page. 46a47a12beSStefan Roese */ 47a47a12beSStefan Roese #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 48a47a12beSStefan Roese #ifndef CONFIG_BPTR_VIRT_ADDR 49a47a12beSStefan Roese #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 50a47a12beSStefan Roese #endif 51a47a12beSStefan Roese #endif 52a47a12beSStefan Roese 53f51cdaf1SBecky Bruce /* Since so many PPC SOCs have a semi-common LBC, define this here */ 54f51cdaf1SBecky Bruce #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 55f51cdaf1SBecky Bruce defined(CONFIG_MPC83xx) 56d789b5f5SDipen Dudhat #if !defined(CONFIG_FSL_IFC) 57f51cdaf1SBecky Bruce #define CONFIG_FSL_LBC 58f51cdaf1SBecky Bruce #endif 59d789b5f5SDipen Dudhat #endif 60f51cdaf1SBecky Bruce 61063c1263SAndy Fleming /* The TSEC driver uses the PHYLIB infrastructure */ 62990d06b0SZhao Qiang #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB) 63063c1263SAndy Fleming #include <config_phylib_all_drivers.h> 64063c1263SAndy Fleming #endif /* TSEC_ENET */ 65063c1263SAndy Fleming 66c916d7c9SKumar Gala /* The FMAN driver uses the PHYLIB infrastructure */ 67c916d7c9SKumar Gala 68f2a37fcdSAlbert Aribaud /* All PPC boards must swap IDE bytes */ 69f2a37fcdSAlbert Aribaud #define CONFIG_IDE_SWAP_IO 70f2a37fcdSAlbert Aribaud 71*07d538d2SMario Six #if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX) 72f27445cbSThomas Chou /* 73f27445cbSThomas Chou * TODO: Convert this to a clock driver exists that can give us the UART 74f27445cbSThomas Chou * clock here. 75f27445cbSThomas Chou */ 76f27445cbSThomas Chou #define CONFIG_SYS_NS16550_CLK get_serial_clock() 77f27445cbSThomas Chou #endif 78f27445cbSThomas Chou 79a47a12beSStefan Roese #endif /* _ASM_CONFIG_H_ */ 80