1*432054b9SJagdish Gediya// SPDX-License-Identifier: GPL-2.0+ OR X11 2*432054b9SJagdish Gediya/* 3*432054b9SJagdish Gediya * T2080/T2081 Silicon/SoC Device Tree Source (pre include) 4*432054b9SJagdish Gediya * 5*432054b9SJagdish Gediya * Copyright 2013 Freescale Semiconductor Inc. 6*432054b9SJagdish Gediya * Copyright 2018 NXP 7*432054b9SJagdish Gediya */ 8*432054b9SJagdish Gediya 9*432054b9SJagdish Gediya/dts-v1/; 10*432054b9SJagdish Gediya 11*432054b9SJagdish Gediya/include/ "e6500_power_isa.dtsi" 12*432054b9SJagdish Gediya 13*432054b9SJagdish Gediya/ { 14*432054b9SJagdish Gediya #address-cells = <2>; 15*432054b9SJagdish Gediya #size-cells = <2>; 16*432054b9SJagdish Gediya interrupt-parent = <&mpic>; 17*432054b9SJagdish Gediya 18*432054b9SJagdish Gediya cpus { 19*432054b9SJagdish Gediya #address-cells = <1>; 20*432054b9SJagdish Gediya #size-cells = <0>; 21*432054b9SJagdish Gediya 22*432054b9SJagdish Gediya cpu0: PowerPC,e6500@0 { 23*432054b9SJagdish Gediya device_type = "cpu"; 24*432054b9SJagdish Gediya reg = <0 1>; 25*432054b9SJagdish Gediya fsl,portid-mapping = <0x80000000>; 26*432054b9SJagdish Gediya }; 27*432054b9SJagdish Gediya cpu1: PowerPC,e6500@2 { 28*432054b9SJagdish Gediya device_type = "cpu"; 29*432054b9SJagdish Gediya reg = <2 3>; 30*432054b9SJagdish Gediya fsl,portid-mapping = <0x80000000>; 31*432054b9SJagdish Gediya }; 32*432054b9SJagdish Gediya cpu2: PowerPC,e6500@4 { 33*432054b9SJagdish Gediya device_type = "cpu"; 34*432054b9SJagdish Gediya reg = <4 5>; 35*432054b9SJagdish Gediya fsl,portid-mapping = <0x80000000>; 36*432054b9SJagdish Gediya }; 37*432054b9SJagdish Gediya cpu3: PowerPC,e6500@6 { 38*432054b9SJagdish Gediya device_type = "cpu"; 39*432054b9SJagdish Gediya reg = <6 7>; 40*432054b9SJagdish Gediya fsl,portid-mapping = <0x80000000>; 41*432054b9SJagdish Gediya }; 42*432054b9SJagdish Gediya }; 43*432054b9SJagdish Gediya 44*432054b9SJagdish Gediya soc: soc@ffe000000 { 45*432054b9SJagdish Gediya ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 46*432054b9SJagdish Gediya reg = <0xf 0xfe000000 0 0x00001000>; 47*432054b9SJagdish Gediya #address-cells = <1>; 48*432054b9SJagdish Gediya #size-cells = <1>; 49*432054b9SJagdish Gediya device_type = "soc"; 50*432054b9SJagdish Gediya compatible = "simple-bus"; 51*432054b9SJagdish Gediya 52*432054b9SJagdish Gediya mpic: pic@40000 { 53*432054b9SJagdish Gediya interrupt-controller; 54*432054b9SJagdish Gediya #address-cells = <0>; 55*432054b9SJagdish Gediya #interrupt-cells = <4>; 56*432054b9SJagdish Gediya reg = <0x40000 0x40000>; 57*432054b9SJagdish Gediya compatible = "fsl,mpic"; 58*432054b9SJagdish Gediya device_type = "open-pic"; 59*432054b9SJagdish Gediya clock-frequency = <0x0>; 60*432054b9SJagdish Gediya }; 61*432054b9SJagdish Gediya }; 62*432054b9SJagdish Gediya}; 63