xref: /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/start.S (revision d937326ffcd6da4c6ba1297a8786cfeaec1812e7) 
1/*
2 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
3 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9/*  U-Boot - Startup Code for PowerPC based Embedded Boards
10 *
11 *
12 *  The processor starts at 0x00000100 and the code is executed
13 *  from flash. The code is organized to be at an other address
14 *  in memory, but as long we don't jump around before relocating,
15 *  board_init lies at a quite high address and when the cpu has
16 *  jumped there, everything is ok.
17 *  This works because the cpu gives the FLASH (CS0) the whole
18 *  address space at startup, and board_init lies as a echo of
19 *  the flash somewhere up there in the memory map.
20 *
21 *  board_init will change CS0 to be positioned at the correct
22 *  address and (s)dram will be positioned at address 0
23 */
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc8xx.h>
27#include <version.h>
28
29#define CONFIG_8xx 1		/* needed for Linux kernel header files */
30
31#include <ppc_asm.tmpl>
32#include <ppc_defs.h>
33
34#include <asm/cache.h>
35#include <asm/mmu.h>
36#include <asm/u-boot.h>
37
38/* We don't want the  MMU yet.
39*/
40#undef	MSR_KERNEL
41#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
42
43/*
44 * Set up GOT: Global Offset Table
45 *
46 * Use r12 to access the GOT
47 */
48	START_GOT
49	GOT_ENTRY(_GOT2_TABLE_)
50	GOT_ENTRY(_FIXUP_TABLE_)
51
52	GOT_ENTRY(_start)
53	GOT_ENTRY(_start_of_vectors)
54	GOT_ENTRY(_end_of_vectors)
55	GOT_ENTRY(transfer_to_handler)
56
57	GOT_ENTRY(__init_end)
58	GOT_ENTRY(__bss_end)
59	GOT_ENTRY(__bss_start)
60	END_GOT
61
62/*
63 * r3 - 1st arg to board_init(): IMMP pointer
64 * r4 - 2nd arg to board_init(): boot flag
65 */
66	.text
67	.long	0x27051956		/* U-Boot Magic Number			*/
68	.globl	version_string
69version_string:
70	.ascii U_BOOT_VERSION_STRING, "\0"
71
72	. = EXC_OFF_SYS_RESET
73	.globl	_start
74_start:
75	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
76	mtspr	638, r3
77
78	/* Initialize machine status; enable machine check interrupt		*/
79	/*----------------------------------------------------------------------*/
80	li	r3, MSR_KERNEL		/* Set ME, RI flags */
81	mtmsr	r3
82	mtspr	SRR1, r3		/* Make SRR1 match MSR */
83
84	mfspr	r3, ICR			/* clear Interrupt Cause Register */
85
86	/* Initialize debug port registers					*/
87	/*----------------------------------------------------------------------*/
88	xor	r0, r0, r0		/* Clear R0 */
89	mtspr	LCTRL1, r0		/* Initialize debug port regs */
90	mtspr	LCTRL2, r0
91	mtspr	COUNTA, r0
92	mtspr	COUNTB, r0
93
94	/* Reset the caches							*/
95	/*----------------------------------------------------------------------*/
96
97	mfspr	r3, IC_CST		/* Clear error bits */
98	mfspr	r3, DC_CST
99
100	lis	r3, IDC_UNALL@h		/* Unlock all */
101	mtspr	IC_CST, r3
102	mtspr	DC_CST, r3
103
104	lis	r3, IDC_INVALL@h	/* Invalidate all */
105	mtspr	IC_CST, r3
106	mtspr	DC_CST, r3
107
108	lis	r3, IDC_DISABLE@h	/* Disable data cache */
109	mtspr	DC_CST, r3
110
111#if !defined(CONFIG_SYS_DELAYED_ICACHE)
112					/* On IP860 and PCU E,
113					 * we cannot enable IC yet
114					 */
115	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
116#endif
117	mtspr	IC_CST, r3
118
119	/* invalidate all tlb's							*/
120	/*----------------------------------------------------------------------*/
121
122	tlbia
123	isync
124
125	/*
126	 * Calculate absolute address in FLASH and jump there
127	 *----------------------------------------------------------------------*/
128
129	lis	r3, CONFIG_SYS_MONITOR_BASE@h
130	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
131	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
132	mtlr	r3
133	blr
134
135in_flash:
136
137	/* initialize some SPRs that are hard to access from C			*/
138	/*----------------------------------------------------------------------*/
139
140	lis	r3, CONFIG_SYS_IMMR@h		/* pass IMMR as arg1 to C routine */
141	ori	r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
142	/* Note: R0 is still 0 here */
143	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
144	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
145
146	/*
147	 * Disable serialized ifetch and show cycles
148	 * (i.e. set processor to normal mode).
149	 * This is also a silicon bug workaround, see errata
150	 */
151
152	li	r2, 0x0007
153	mtspr	ICTRL, r2
154
155	/* Set up debug mode entry */
156
157	lis	r2, CONFIG_SYS_DER@h
158	ori	r2, r2, CONFIG_SYS_DER@l
159	mtspr	DER, r2
160
161	/* let the C-code set up the rest					*/
162	/*									*/
163	/* Be careful to keep code relocatable !				*/
164	/*----------------------------------------------------------------------*/
165
166	GET_GOT			/* initialize GOT access			*/
167
168	/* r3: IMMR */
169	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
170
171	bl	board_init_f	/* run 1st part of board init code (from Flash) */
172
173	/* NOTREACHED - board_init_f() does not return */
174
175
176	.globl	_start_of_vectors
177_start_of_vectors:
178
179/* Machine check */
180	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
181
182/* Data Storage exception.  "Never" generated on the 860. */
183	STD_EXCEPTION(0x300, DataStorage, UnknownException)
184
185/* Instruction Storage exception.  "Never" generated on the 860. */
186	STD_EXCEPTION(0x400, InstStorage, UnknownException)
187
188/* External Interrupt exception. */
189	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
190
191/* Alignment exception. */
192	. = 0x600
193Alignment:
194	EXCEPTION_PROLOG(SRR0, SRR1)
195	mfspr	r4,DAR
196	stw	r4,_DAR(r21)
197	mfspr	r5,DSISR
198	stw	r5,_DSISR(r21)
199	addi	r3,r1,STACK_FRAME_OVERHEAD
200	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
201
202/* Program check exception */
203	. = 0x700
204ProgramCheck:
205	EXCEPTION_PROLOG(SRR0, SRR1)
206	addi	r3,r1,STACK_FRAME_OVERHEAD
207	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
208		MSR_KERNEL, COPY_EE)
209
210	/* No FPU on MPC8xx.  This exception is not supposed to happen.
211	*/
212	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
213
214	/* I guess we could implement decrementer, and may have
215	 * to someday for timekeeping.
216	 */
217	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
218	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
219	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
220	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
221	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
222
223	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
224	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
225
226	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
227	 * for all unimplemented and illegal instructions.
228	 */
229	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
230
231	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
232	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
233	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
234	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
235
236	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
237	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
238	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
239	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
240	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
241	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
242	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
243
244	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
245	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
246	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
247	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
248
249
250	.globl	_end_of_vectors
251_end_of_vectors:
252
253
254	. = 0x2000
255
256/*
257 * This code finishes saving the registers to the exception frame
258 * and jumps to the appropriate handler for the exception.
259 * Register r21 is pointer into trap frame, r1 has new stack pointer.
260 */
261	.globl	transfer_to_handler
262transfer_to_handler:
263	stw	r22,_NIP(r21)
264	lis	r22,MSR_POW@h
265	andc	r23,r23,r22
266	stw	r23,_MSR(r21)
267	SAVE_GPR(7, r21)
268	SAVE_4GPRS(8, r21)
269	SAVE_8GPRS(12, r21)
270	SAVE_8GPRS(24, r21)
271	mflr	r23
272	andi.	r24,r23,0x3f00		/* get vector offset */
273	stw	r24,TRAP(r21)
274	li	r22,0
275	stw	r22,RESULT(r21)
276	mtspr	SPRG2,r22		/* r1 is now kernel sp */
277	lwz	r24,0(r23)		/* virtual address of handler */
278	lwz	r23,4(r23)		/* where to go when done */
279	mtspr	SRR0,r24
280	mtspr	SRR1,r20
281	mtlr	r23
282	SYNC
283	rfi				/* jump to handler, enable MMU */
284
285int_return:
286	mfmsr	r28			/* Disable interrupts */
287	li	r4,0
288	ori	r4,r4,MSR_EE
289	andc	r28,r28,r4
290	SYNC				/* Some chip revs need this... */
291	mtmsr	r28
292	SYNC
293	lwz	r2,_CTR(r1)
294	lwz	r0,_LINK(r1)
295	mtctr	r2
296	mtlr	r0
297	lwz	r2,_XER(r1)
298	lwz	r0,_CCR(r1)
299	mtspr	XER,r2
300	mtcrf	0xFF,r0
301	REST_10GPRS(3, r1)
302	REST_10GPRS(13, r1)
303	REST_8GPRS(23, r1)
304	REST_GPR(31, r1)
305	lwz	r2,_NIP(r1)		/* Restore environment */
306	lwz	r0,_MSR(r1)
307	mtspr	SRR0,r2
308	mtspr	SRR1,r0
309	lwz	r0,GPR0(r1)
310	lwz	r2,GPR2(r1)
311	lwz	r1,GPR1(r1)
312	SYNC
313	rfi
314
315/* Cache functions.
316*/
317	.globl	icache_enable
318icache_enable:
319	SYNC
320	lis	r3, IDC_INVALL@h
321	mtspr	IC_CST, r3
322	lis	r3, IDC_ENABLE@h
323	mtspr	IC_CST, r3
324	blr
325
326	.globl	icache_disable
327icache_disable:
328	SYNC
329	lis	r3, IDC_DISABLE@h
330	mtspr	IC_CST, r3
331	blr
332
333	.globl	icache_status
334icache_status:
335	mfspr	r3, IC_CST
336	srwi	r3, r3, 31	/* >>31 => select bit 0 */
337	blr
338
339	.globl	dcache_enable
340dcache_enable:
341#if 0
342	SYNC
343#endif
344#if 1
345	lis	r3, 0x0400		/* Set cache mode with MMU off */
346	mtspr	MD_CTR, r3
347#endif
348
349	lis	r3, IDC_INVALL@h
350	mtspr	DC_CST, r3
351#if 0
352	lis	r3, DC_SFWT@h
353	mtspr	DC_CST, r3
354#endif
355	lis	r3, IDC_ENABLE@h
356	mtspr	DC_CST, r3
357	blr
358
359	.globl	dcache_disable
360dcache_disable:
361	SYNC
362	lis	r3, IDC_DISABLE@h
363	mtspr	DC_CST, r3
364	lis	r3, IDC_INVALL@h
365	mtspr	DC_CST, r3
366	blr
367
368	.globl	dcache_status
369dcache_status:
370	mfspr	r3, DC_CST
371	srwi	r3, r3, 31	/* >>31 => select bit 0 */
372	blr
373
374	.globl	dc_read
375dc_read:
376	mtspr	DC_ADR, r3
377	mfspr	r3, DC_DAT
378	blr
379
380/*
381 * unsigned int get_immr (unsigned int mask)
382 *
383 * return (mask ? (IMMR & mask) : IMMR);
384 */
385	.globl	get_immr
386get_immr:
387	mr	r4,r3		/* save mask */
388	mfspr	r3, IMMR	/* IMMR */
389	cmpwi	0,r4,0		/* mask != 0 ? */
390	beq	4f
391	and	r3,r3,r4	/* IMMR & mask */
3924:
393	blr
394
395	.globl get_pvr
396get_pvr:
397	mfspr	r3, PVR
398	blr
399
400
401	.globl wr_ic_cst
402wr_ic_cst:
403	mtspr	IC_CST, r3
404	blr
405
406	.globl rd_ic_cst
407rd_ic_cst:
408	mfspr	r3, IC_CST
409	blr
410
411	.globl wr_ic_adr
412wr_ic_adr:
413	mtspr	IC_ADR, r3
414	blr
415
416
417	.globl wr_dc_cst
418wr_dc_cst:
419	mtspr	DC_CST, r3
420	blr
421
422	.globl rd_dc_cst
423rd_dc_cst:
424	mfspr	r3, DC_CST
425	blr
426
427	.globl wr_dc_adr
428wr_dc_adr:
429	mtspr	DC_ADR, r3
430	blr
431
432/*------------------------------------------------------------------------------*/
433
434/*
435 * void relocate_code (addr_sp, gd, addr_moni)
436 *
437 * This "function" does not return, instead it continues in RAM
438 * after relocating the monitor code.
439 *
440 * r3 = dest
441 * r4 = src
442 * r5 = length in bytes
443 * r6 = cachelinesize
444 */
445	.globl	relocate_code
446relocate_code:
447	mr	r1,  r3		/* Set new stack pointer		*/
448	mr	r9,  r4		/* Save copy of Global Data pointer	*/
449	mr	r10, r5		/* Save copy of Destination Address	*/
450
451	GET_GOT
452	mr	r3,  r5				/* Destination Address	*/
453	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
454	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
455	lwz	r5, GOT(__init_end)
456	sub	r5, r5, r4
457	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
458
459	/*
460	 * Fix GOT pointer:
461	 *
462	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
463	 *
464	 * Offset:
465	 */
466	sub	r15, r10, r4
467
468	/* First our own GOT */
469	add	r12, r12, r15
470	/* then the one used by the C code */
471	add	r30, r30, r15
472
473	/*
474	 * Now relocate code
475	 */
476
477	cmplw	cr1,r3,r4
478	addi	r0,r5,3
479	srwi.	r0,r0,2
480	beq	cr1,4f		/* In place copy is not necessary	*/
481	beq	7f		/* Protect against 0 count		*/
482	mtctr	r0
483	bge	cr1,2f
484
485	la	r8,-4(r4)
486	la	r7,-4(r3)
4871:	lwzu	r0,4(r8)
488	stwu	r0,4(r7)
489	bdnz	1b
490	b	4f
491
4922:	slwi	r0,r0,2
493	add	r8,r4,r0
494	add	r7,r3,r0
4953:	lwzu	r0,-4(r8)
496	stwu	r0,-4(r7)
497	bdnz	3b
498
499/*
500 * Now flush the cache: note that we must start from a cache aligned
501 * address. Otherwise we might miss one cache line.
502 */
5034:	cmpwi	r6,0
504	add	r5,r3,r5
505	beq	7f		/* Always flush prefetch queue in any case */
506	subi	r0,r6,1
507	andc	r3,r3,r0
508	mr	r4,r3
5095:	dcbst	0,r4
510	add	r4,r4,r6
511	cmplw	r4,r5
512	blt	5b
513	sync			/* Wait for all dcbst to complete on bus */
514	mr	r4,r3
5156:	icbi	0,r4
516	add	r4,r4,r6
517	cmplw	r4,r5
518	blt	6b
5197:	sync			/* Wait for all icbi to complete on bus	*/
520	isync
521
522/*
523 * We are done. Do not return, instead branch to second part of board
524 * initialization, now running from RAM.
525 */
526
527	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
528	mtlr	r0
529	blr
530
531in_ram:
532
533	/*
534	 * Relocation Function, r12 point to got2+0x8000
535	 *
536	 * Adjust got2 pointers, no need to check for 0, this code
537	 * already puts a few entries in the table.
538	 */
539	li	r0,__got2_entries@sectoff@l
540	la	r3,GOT(_GOT2_TABLE_)
541	lwz	r11,GOT(_GOT2_TABLE_)
542	mtctr	r0
543	sub	r11,r3,r11
544	addi	r3,r3,-4
5451:	lwzu	r0,4(r3)
546	cmpwi	r0,0
547	beq-	2f
548	add	r0,r0,r11
549	stw	r0,0(r3)
5502:	bdnz	1b
551
552	/*
553	 * Now adjust the fixups and the pointers to the fixups
554	 * in case we need to move ourselves again.
555	 */
556	li	r0,__fixup_entries@sectoff@l
557	lwz	r3,GOT(_FIXUP_TABLE_)
558	cmpwi	r0,0
559	mtctr	r0
560	addi	r3,r3,-4
561	beq	4f
5623:	lwzu	r4,4(r3)
563	lwzux	r0,r4,r11
564	cmpwi	r0,0
565	add	r0,r0,r11
566	stw	r4,0(r3)
567	beq-	5f
568	stw	r0,0(r4)
5695:	bdnz	3b
5704:
571clear_bss:
572	/*
573	 * Now clear BSS segment
574	 */
575	lwz	r3,GOT(__bss_start)
576	lwz	r4,GOT(__bss_end)
577
578	cmplw	0, r3, r4
579	beq	6f
580
581	li	r0, 0
5825:
583	stw	r0, 0(r3)
584	addi	r3, r3, 4
585	cmplw	0, r3, r4
586	bne	5b
5876:
588
589	mr	r3, r9		/* Global Data pointer		*/
590	mr	r4, r10		/* Destination Address		*/
591	bl	board_init_r
592
593	/*
594	 * Copy exception vector code to low memory
595	 *
596	 * r3: dest_addr
597	 * r7: source address, r8: end address, r9: target address
598	 */
599	.globl	trap_init
600trap_init:
601	mflr	r4			/* save link register		*/
602	GET_GOT
603	lwz	r7, GOT(_start)
604	lwz	r8, GOT(_end_of_vectors)
605
606	li	r9, 0x100		/* reset vector always at 0x100 */
607
608	cmplw	0, r7, r8
609	bgelr				/* return if r7>=r8 - just in case */
6101:
611	lwz	r0, 0(r7)
612	stw	r0, 0(r9)
613	addi	r7, r7, 4
614	addi	r9, r9, 4
615	cmplw	0, r7, r8
616	bne	1b
617
618	/*
619	 * relocate `hdlr' and `int_return' entries
620	 */
621	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
622	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
6232:
624	bl	trap_reloc
625	addi	r7, r7, 0x100		/* next exception vector	*/
626	cmplw	0, r7, r8
627	blt	2b
628
629	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
630	bl	trap_reloc
631
632	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
633	bl	trap_reloc
634
635	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
636	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
6373:
638	bl	trap_reloc
639	addi	r7, r7, 0x100		/* next exception vector	*/
640	cmplw	0, r7, r8
641	blt	3b
642
643	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
644	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
6454:
646	bl	trap_reloc
647	addi	r7, r7, 0x100		/* next exception vector	*/
648	cmplw	0, r7, r8
649	blt	4b
650
651	mtlr	r4			/* restore link register	*/
652	blr
653