xref: /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/start.S (revision 9925f1dbc38c0ef7220c6fca5968c708b8e48764) 
1/*
2 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
3 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9/*  U-Boot - Startup Code for PowerPC based Embedded Boards
10 *
11 *
12 *  The processor starts at 0x00000100 and the code is executed
13 *  from flash. The code is organized to be at an other address
14 *  in memory, but as long we don't jump around before relocating,
15 *  board_init lies at a quite high address and when the cpu has
16 *  jumped there, everything is ok.
17 *  This works because the cpu gives the FLASH (CS0) the whole
18 *  address space at startup, and board_init lies as a echo of
19 *  the flash somewhere up there in the memory map.
20 *
21 *  board_init will change CS0 to be positioned at the correct
22 *  address and (s)dram will be positioned at address 0
23 */
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc8xx.h>
27#include <version.h>
28
29#include <ppc_asm.tmpl>
30#include <ppc_defs.h>
31
32#include <asm/cache.h>
33#include <asm/mmu.h>
34#include <asm/u-boot.h>
35
36/* We don't want the  MMU yet.
37*/
38#undef	MSR_KERNEL
39#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
40
41/*
42 * Set up GOT: Global Offset Table
43 *
44 * Use r12 to access the GOT
45 */
46	START_GOT
47	GOT_ENTRY(_GOT2_TABLE_)
48	GOT_ENTRY(_FIXUP_TABLE_)
49
50	GOT_ENTRY(_start)
51	GOT_ENTRY(_start_of_vectors)
52	GOT_ENTRY(_end_of_vectors)
53	GOT_ENTRY(transfer_to_handler)
54
55	GOT_ENTRY(__init_end)
56	GOT_ENTRY(__bss_end)
57	GOT_ENTRY(__bss_start)
58	END_GOT
59
60/*
61 * r3 - 1st arg to board_init(): IMMP pointer
62 * r4 - 2nd arg to board_init(): boot flag
63 */
64	.text
65	.long	0x27051956		/* U-Boot Magic Number			*/
66	.globl	version_string
67version_string:
68	.ascii U_BOOT_VERSION_STRING, "\0"
69
70	. = EXC_OFF_SYS_RESET
71	.globl	_start
72_start:
73	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
74	mtspr	638, r3
75
76	/* Initialize machine status; enable machine check interrupt		*/
77	/*----------------------------------------------------------------------*/
78	li	r3, MSR_KERNEL		/* Set ME, RI flags */
79	mtmsr	r3
80	mtspr	SRR1, r3		/* Make SRR1 match MSR */
81
82	mfspr	r3, ICR			/* clear Interrupt Cause Register */
83
84	/* Initialize debug port registers					*/
85	/*----------------------------------------------------------------------*/
86	xor	r0, r0, r0		/* Clear R0 */
87	mtspr	LCTRL1, r0		/* Initialize debug port regs */
88	mtspr	LCTRL2, r0
89	mtspr	COUNTA, r0
90	mtspr	COUNTB, r0
91
92	/* Reset the caches							*/
93	/*----------------------------------------------------------------------*/
94
95	mfspr	r3, IC_CST		/* Clear error bits */
96	mfspr	r3, DC_CST
97
98	lis	r3, IDC_UNALL@h		/* Unlock all */
99	mtspr	IC_CST, r3
100	mtspr	DC_CST, r3
101
102	lis	r3, IDC_INVALL@h	/* Invalidate all */
103	mtspr	IC_CST, r3
104	mtspr	DC_CST, r3
105
106	lis	r3, IDC_DISABLE@h	/* Disable data cache */
107	mtspr	DC_CST, r3
108
109	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
110	mtspr	IC_CST, r3
111
112	/* invalidate all tlb's							*/
113	/*----------------------------------------------------------------------*/
114
115	tlbia
116	isync
117
118	/*
119	 * Calculate absolute address in FLASH and jump there
120	 *----------------------------------------------------------------------*/
121
122	lis	r3, CONFIG_SYS_MONITOR_BASE@h
123	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
124	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
125	mtlr	r3
126	blr
127
128in_flash:
129
130	/* initialize some SPRs that are hard to access from C			*/
131	/*----------------------------------------------------------------------*/
132
133	/*
134	 * Disable serialized ifetch and show cycles
135	 * (i.e. set processor to normal mode).
136	 * This is also a silicon bug workaround, see errata
137	 */
138
139	li	r2, 0x0007
140	mtspr	ICTRL, r2
141
142	/* Set up debug mode entry */
143
144	lis	r2, CONFIG_SYS_DER@h
145	ori	r2, r2, CONFIG_SYS_DER@l
146	mtspr	DER, r2
147
148	/* set up the stack in internal DPRAM */
149	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
150	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
151	addi	r1, r3, -8
152
153	bl	board_init_f_alloc_reserve
154	addi	r1, r3, -8
155
156	/* Zeroise the CPM dpram */
157	lis	r4, CONFIG_SYS_IMMR@h
158	ori	r4, r4, (0x2000 - 4)
159	li	r0, (0x2000 / 4)
160	mtctr	r0
161	li	r0, 0
1621:	stwu	r0, 4(r4)
163	bdnz	1b
164
165	bl	board_init_f_init_reserve
166
167	/* let the C-code set up the rest					*/
168	/*									*/
169	/* Be careful to keep code relocatable !				*/
170	/*----------------------------------------------------------------------*/
171
172	GET_GOT			/* initialize GOT access			*/
173
174	lis	r3, CONFIG_SYS_IMMR@h
175	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
176
177	bl	board_init_f	/* run 1st part of board init code (from Flash) */
178
179	/* NOTREACHED - board_init_f() does not return */
180
181
182	.globl	_start_of_vectors
183_start_of_vectors:
184
185/* Machine check */
186	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
187
188/* Data Storage exception.  "Never" generated on the 860. */
189	STD_EXCEPTION(0x300, DataStorage, UnknownException)
190
191/* Instruction Storage exception.  "Never" generated on the 860. */
192	STD_EXCEPTION(0x400, InstStorage, UnknownException)
193
194/* External Interrupt exception. */
195	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
196
197/* Alignment exception. */
198	. = 0x600
199Alignment:
200	EXCEPTION_PROLOG(SRR0, SRR1)
201	mfspr	r4,DAR
202	stw	r4,_DAR(r21)
203	mfspr	r5,DSISR
204	stw	r5,_DSISR(r21)
205	addi	r3,r1,STACK_FRAME_OVERHEAD
206	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
207
208/* Program check exception */
209	. = 0x700
210ProgramCheck:
211	EXCEPTION_PROLOG(SRR0, SRR1)
212	addi	r3,r1,STACK_FRAME_OVERHEAD
213	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
214		MSR_KERNEL, COPY_EE)
215
216	/* No FPU on MPC8xx.  This exception is not supposed to happen.
217	*/
218	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
219
220	/* I guess we could implement decrementer, and may have
221	 * to someday for timekeeping.
222	 */
223	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
224	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
225	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
226	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
227	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
228
229	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
230	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
231
232	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
233	 * for all unimplemented and illegal instructions.
234	 */
235	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
236
237	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
238	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
239	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
240	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
241
242	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
243	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
244	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
245	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
246	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
247	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
248	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
249
250	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
251	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
252	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
253	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
254
255
256	.globl	_end_of_vectors
257_end_of_vectors:
258
259
260	. = 0x2000
261
262/*
263 * This code finishes saving the registers to the exception frame
264 * and jumps to the appropriate handler for the exception.
265 * Register r21 is pointer into trap frame, r1 has new stack pointer.
266 */
267	.globl	transfer_to_handler
268transfer_to_handler:
269	stw	r22,_NIP(r21)
270	lis	r22,MSR_POW@h
271	andc	r23,r23,r22
272	stw	r23,_MSR(r21)
273	SAVE_GPR(7, r21)
274	SAVE_4GPRS(8, r21)
275	SAVE_8GPRS(12, r21)
276	SAVE_8GPRS(24, r21)
277	mflr	r23
278	andi.	r24,r23,0x3f00		/* get vector offset */
279	stw	r24,TRAP(r21)
280	li	r22,0
281	stw	r22,RESULT(r21)
282	mtspr	SPRG2,r22		/* r1 is now kernel sp */
283	lwz	r24,0(r23)		/* virtual address of handler */
284	lwz	r23,4(r23)		/* where to go when done */
285	mtspr	SRR0,r24
286	mtspr	SRR1,r20
287	mtlr	r23
288	SYNC
289	rfi				/* jump to handler, enable MMU */
290
291int_return:
292	mfmsr	r28			/* Disable interrupts */
293	li	r4,0
294	ori	r4,r4,MSR_EE
295	andc	r28,r28,r4
296	SYNC				/* Some chip revs need this... */
297	mtmsr	r28
298	SYNC
299	lwz	r2,_CTR(r1)
300	lwz	r0,_LINK(r1)
301	mtctr	r2
302	mtlr	r0
303	lwz	r2,_XER(r1)
304	lwz	r0,_CCR(r1)
305	mtspr	XER,r2
306	mtcrf	0xFF,r0
307	REST_10GPRS(3, r1)
308	REST_10GPRS(13, r1)
309	REST_8GPRS(23, r1)
310	REST_GPR(31, r1)
311	lwz	r2,_NIP(r1)		/* Restore environment */
312	lwz	r0,_MSR(r1)
313	mtspr	SRR0,r2
314	mtspr	SRR1,r0
315	lwz	r0,GPR0(r1)
316	lwz	r2,GPR2(r1)
317	lwz	r1,GPR1(r1)
318	SYNC
319	rfi
320
321/*------------------------------------------------------------------------------*/
322
323/*
324 * void relocate_code (addr_sp, gd, addr_moni)
325 *
326 * This "function" does not return, instead it continues in RAM
327 * after relocating the monitor code.
328 *
329 * r3 = dest
330 * r4 = src
331 * r5 = length in bytes
332 * r6 = cachelinesize
333 */
334	.globl	relocate_code
335relocate_code:
336	mr	r1,  r3		/* Set new stack pointer		*/
337	mr	r9,  r4		/* Save copy of Global Data pointer	*/
338	mr	r10, r5		/* Save copy of Destination Address	*/
339
340	GET_GOT
341	mr	r3,  r5				/* Destination Address	*/
342	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
343	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
344	lwz	r5, GOT(__init_end)
345	sub	r5, r5, r4
346	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
347
348	/*
349	 * Fix GOT pointer:
350	 *
351	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
352	 *
353	 * Offset:
354	 */
355	sub	r15, r10, r4
356
357	/* First our own GOT */
358	add	r12, r12, r15
359	/* then the one used by the C code */
360	add	r30, r30, r15
361
362	/*
363	 * Now relocate code
364	 */
365
366	cmplw	cr1,r3,r4
367	addi	r0,r5,3
368	srwi.	r0,r0,2
369	beq	cr1,4f		/* In place copy is not necessary	*/
370	beq	7f		/* Protect against 0 count		*/
371	mtctr	r0
372	bge	cr1,2f
373
374	la	r8,-4(r4)
375	la	r7,-4(r3)
3761:	lwzu	r0,4(r8)
377	stwu	r0,4(r7)
378	bdnz	1b
379	b	4f
380
3812:	slwi	r0,r0,2
382	add	r8,r4,r0
383	add	r7,r3,r0
3843:	lwzu	r0,-4(r8)
385	stwu	r0,-4(r7)
386	bdnz	3b
387
388/*
389 * Now flush the cache: note that we must start from a cache aligned
390 * address. Otherwise we might miss one cache line.
391 */
3924:	cmpwi	r6,0
393	add	r5,r3,r5
394	beq	7f		/* Always flush prefetch queue in any case */
395	subi	r0,r6,1
396	andc	r3,r3,r0
397	mr	r4,r3
3985:	dcbst	0,r4
399	add	r4,r4,r6
400	cmplw	r4,r5
401	blt	5b
402	sync			/* Wait for all dcbst to complete on bus */
403	mr	r4,r3
4046:	icbi	0,r4
405	add	r4,r4,r6
406	cmplw	r4,r5
407	blt	6b
4087:	sync			/* Wait for all icbi to complete on bus	*/
409	isync
410
411/*
412 * We are done. Do not return, instead branch to second part of board
413 * initialization, now running from RAM.
414 */
415
416	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
417	mtlr	r0
418	blr
419
420in_ram:
421
422	/*
423	 * Relocation Function, r12 point to got2+0x8000
424	 *
425	 * Adjust got2 pointers, no need to check for 0, this code
426	 * already puts a few entries in the table.
427	 */
428	li	r0,__got2_entries@sectoff@l
429	la	r3,GOT(_GOT2_TABLE_)
430	lwz	r11,GOT(_GOT2_TABLE_)
431	mtctr	r0
432	sub	r11,r3,r11
433	addi	r3,r3,-4
4341:	lwzu	r0,4(r3)
435	cmpwi	r0,0
436	beq-	2f
437	add	r0,r0,r11
438	stw	r0,0(r3)
4392:	bdnz	1b
440
441	/*
442	 * Now adjust the fixups and the pointers to the fixups
443	 * in case we need to move ourselves again.
444	 */
445	li	r0,__fixup_entries@sectoff@l
446	lwz	r3,GOT(_FIXUP_TABLE_)
447	cmpwi	r0,0
448	mtctr	r0
449	addi	r3,r3,-4
450	beq	4f
4513:	lwzu	r4,4(r3)
452	lwzux	r0,r4,r11
453	cmpwi	r0,0
454	add	r0,r0,r11
455	stw	r4,0(r3)
456	beq-	5f
457	stw	r0,0(r4)
4585:	bdnz	3b
4594:
460clear_bss:
461	/*
462	 * Now clear BSS segment
463	 */
464	lwz	r3,GOT(__bss_start)
465	lwz	r4,GOT(__bss_end)
466
467	cmplw	0, r3, r4
468	beq	6f
469
470	li	r0, 0
4715:
472	stw	r0, 0(r3)
473	addi	r3, r3, 4
474	cmplw	0, r3, r4
475	bne	5b
4766:
477
478	mr	r3, r9		/* Global Data pointer		*/
479	mr	r4, r10		/* Destination Address		*/
480	bl	board_init_r
481
482	/*
483	 * Copy exception vector code to low memory
484	 *
485	 * r3: dest_addr
486	 * r7: source address, r8: end address, r9: target address
487	 */
488	.globl	trap_init
489trap_init:
490	mflr	r4			/* save link register		*/
491	GET_GOT
492	lwz	r7, GOT(_start)
493	lwz	r8, GOT(_end_of_vectors)
494
495	li	r9, 0x100		/* reset vector always at 0x100 */
496
497	cmplw	0, r7, r8
498	bgelr				/* return if r7>=r8 - just in case */
4991:
500	lwz	r0, 0(r7)
501	stw	r0, 0(r9)
502	addi	r7, r7, 4
503	addi	r9, r9, 4
504	cmplw	0, r7, r8
505	bne	1b
506
507	/*
508	 * relocate `hdlr' and `int_return' entries
509	 */
510	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
511	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
5122:
513	bl	trap_reloc
514	addi	r7, r7, 0x100		/* next exception vector	*/
515	cmplw	0, r7, r8
516	blt	2b
517
518	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
519	bl	trap_reloc
520
521	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
522	bl	trap_reloc
523
524	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
525	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
5263:
527	bl	trap_reloc
528	addi	r7, r7, 0x100		/* next exception vector	*/
529	cmplw	0, r7, r8
530	blt	3b
531
532	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
533	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
5344:
535	bl	trap_reloc
536	addi	r7, r7, 0x100		/* next exception vector	*/
537	cmplw	0, r7, r8
538	blt	4b
539
540	mtlr	r4			/* restore link register	*/
541	blr
542