xref: /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/start.S (revision 506cb8be7e83d29b316e1708bcf05359be16cfb7) 
1/*
2 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
3 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9/*  U-Boot - Startup Code for PowerPC based Embedded Boards
10 *
11 *
12 *  The processor starts at 0x00000100 and the code is executed
13 *  from flash. The code is organized to be at an other address
14 *  in memory, but as long we don't jump around before relocating,
15 *  board_init lies at a quite high address and when the cpu has
16 *  jumped there, everything is ok.
17 *  This works because the cpu gives the FLASH (CS0) the whole
18 *  address space at startup, and board_init lies as a echo of
19 *  the flash somewhere up there in the memory map.
20 *
21 *  board_init will change CS0 to be positioned at the correct
22 *  address and (s)dram will be positioned at address 0
23 */
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc8xx.h>
27#include <version.h>
28
29#include <ppc_asm.tmpl>
30#include <ppc_defs.h>
31
32#include <asm/cache.h>
33#include <asm/mmu.h>
34#include <asm/u-boot.h>
35
36/* We don't want the  MMU yet.
37*/
38#undef	MSR_KERNEL
39#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
40
41/*
42 * Set up GOT: Global Offset Table
43 *
44 * Use r12 to access the GOT
45 */
46	START_GOT
47	GOT_ENTRY(_GOT2_TABLE_)
48	GOT_ENTRY(_FIXUP_TABLE_)
49
50	GOT_ENTRY(_start)
51	GOT_ENTRY(_start_of_vectors)
52	GOT_ENTRY(_end_of_vectors)
53	GOT_ENTRY(transfer_to_handler)
54
55	GOT_ENTRY(__init_end)
56	GOT_ENTRY(__bss_end)
57	GOT_ENTRY(__bss_start)
58	END_GOT
59
60/*
61 * r3 - 1st arg to board_init(): IMMP pointer
62 * r4 - 2nd arg to board_init(): boot flag
63 */
64	.text
65	.long	0x27051956		/* U-Boot Magic Number			*/
66	.globl	version_string
67version_string:
68	.ascii U_BOOT_VERSION_STRING, "\0"
69
70	. = EXC_OFF_SYS_RESET
71	.globl	_start
72_start:
73	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
74	mtspr	638, r3
75
76	/* Initialize machine status; enable machine check interrupt		*/
77	/*----------------------------------------------------------------------*/
78	li	r3, MSR_KERNEL		/* Set ME, RI flags */
79	mtmsr	r3
80	mtspr	SRR1, r3		/* Make SRR1 match MSR */
81
82	mfspr	r3, ICR			/* clear Interrupt Cause Register */
83
84	/* Initialize debug port registers					*/
85	/*----------------------------------------------------------------------*/
86	xor	r0, r0, r0		/* Clear R0 */
87	mtspr	LCTRL1, r0		/* Initialize debug port regs */
88	mtspr	LCTRL2, r0
89	mtspr	COUNTA, r0
90	mtspr	COUNTB, r0
91
92	/* Reset the caches							*/
93	/*----------------------------------------------------------------------*/
94
95	mfspr	r3, IC_CST		/* Clear error bits */
96	mfspr	r3, DC_CST
97
98	lis	r3, IDC_UNALL@h		/* Unlock all */
99	mtspr	IC_CST, r3
100	mtspr	DC_CST, r3
101
102	lis	r3, IDC_INVALL@h	/* Invalidate all */
103	mtspr	IC_CST, r3
104	mtspr	DC_CST, r3
105
106	lis	r3, IDC_DISABLE@h	/* Disable data cache */
107	mtspr	DC_CST, r3
108
109	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
110	mtspr	IC_CST, r3
111
112	/* invalidate all tlb's							*/
113	/*----------------------------------------------------------------------*/
114
115	tlbia
116	isync
117
118	/*
119	 * Calculate absolute address in FLASH and jump there
120	 *----------------------------------------------------------------------*/
121
122	lis	r3, CONFIG_SYS_MONITOR_BASE@h
123	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
124	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
125	mtlr	r3
126	blr
127
128in_flash:
129
130	/* initialize some SPRs that are hard to access from C			*/
131	/*----------------------------------------------------------------------*/
132
133	lis	r3, CONFIG_SYS_IMMR@h		/* pass IMMR as arg1 to C routine */
134	ori	r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
135	/* Note: R0 is still 0 here */
136	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
137	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
138
139	/*
140	 * Disable serialized ifetch and show cycles
141	 * (i.e. set processor to normal mode).
142	 * This is also a silicon bug workaround, see errata
143	 */
144
145	li	r2, 0x0007
146	mtspr	ICTRL, r2
147
148	/* Set up debug mode entry */
149
150	lis	r2, CONFIG_SYS_DER@h
151	ori	r2, r2, CONFIG_SYS_DER@l
152	mtspr	DER, r2
153
154	/* let the C-code set up the rest					*/
155	/*									*/
156	/* Be careful to keep code relocatable !				*/
157	/*----------------------------------------------------------------------*/
158
159	GET_GOT			/* initialize GOT access			*/
160
161	/* r3: IMMR */
162	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
163
164	bl	board_init_f	/* run 1st part of board init code (from Flash) */
165
166	/* NOTREACHED - board_init_f() does not return */
167
168
169	.globl	_start_of_vectors
170_start_of_vectors:
171
172/* Machine check */
173	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
174
175/* Data Storage exception.  "Never" generated on the 860. */
176	STD_EXCEPTION(0x300, DataStorage, UnknownException)
177
178/* Instruction Storage exception.  "Never" generated on the 860. */
179	STD_EXCEPTION(0x400, InstStorage, UnknownException)
180
181/* External Interrupt exception. */
182	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
183
184/* Alignment exception. */
185	. = 0x600
186Alignment:
187	EXCEPTION_PROLOG(SRR0, SRR1)
188	mfspr	r4,DAR
189	stw	r4,_DAR(r21)
190	mfspr	r5,DSISR
191	stw	r5,_DSISR(r21)
192	addi	r3,r1,STACK_FRAME_OVERHEAD
193	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
194
195/* Program check exception */
196	. = 0x700
197ProgramCheck:
198	EXCEPTION_PROLOG(SRR0, SRR1)
199	addi	r3,r1,STACK_FRAME_OVERHEAD
200	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
201		MSR_KERNEL, COPY_EE)
202
203	/* No FPU on MPC8xx.  This exception is not supposed to happen.
204	*/
205	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
206
207	/* I guess we could implement decrementer, and may have
208	 * to someday for timekeeping.
209	 */
210	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
211	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
212	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
213	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
214	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
215
216	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
217	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
218
219	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
220	 * for all unimplemented and illegal instructions.
221	 */
222	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
223
224	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
225	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
226	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
227	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
228
229	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
230	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
231	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
232	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
233	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
234	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
235	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
236
237	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
238	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
239	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
240	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
241
242
243	.globl	_end_of_vectors
244_end_of_vectors:
245
246
247	. = 0x2000
248
249/*
250 * This code finishes saving the registers to the exception frame
251 * and jumps to the appropriate handler for the exception.
252 * Register r21 is pointer into trap frame, r1 has new stack pointer.
253 */
254	.globl	transfer_to_handler
255transfer_to_handler:
256	stw	r22,_NIP(r21)
257	lis	r22,MSR_POW@h
258	andc	r23,r23,r22
259	stw	r23,_MSR(r21)
260	SAVE_GPR(7, r21)
261	SAVE_4GPRS(8, r21)
262	SAVE_8GPRS(12, r21)
263	SAVE_8GPRS(24, r21)
264	mflr	r23
265	andi.	r24,r23,0x3f00		/* get vector offset */
266	stw	r24,TRAP(r21)
267	li	r22,0
268	stw	r22,RESULT(r21)
269	mtspr	SPRG2,r22		/* r1 is now kernel sp */
270	lwz	r24,0(r23)		/* virtual address of handler */
271	lwz	r23,4(r23)		/* where to go when done */
272	mtspr	SRR0,r24
273	mtspr	SRR1,r20
274	mtlr	r23
275	SYNC
276	rfi				/* jump to handler, enable MMU */
277
278int_return:
279	mfmsr	r28			/* Disable interrupts */
280	li	r4,0
281	ori	r4,r4,MSR_EE
282	andc	r28,r28,r4
283	SYNC				/* Some chip revs need this... */
284	mtmsr	r28
285	SYNC
286	lwz	r2,_CTR(r1)
287	lwz	r0,_LINK(r1)
288	mtctr	r2
289	mtlr	r0
290	lwz	r2,_XER(r1)
291	lwz	r0,_CCR(r1)
292	mtspr	XER,r2
293	mtcrf	0xFF,r0
294	REST_10GPRS(3, r1)
295	REST_10GPRS(13, r1)
296	REST_8GPRS(23, r1)
297	REST_GPR(31, r1)
298	lwz	r2,_NIP(r1)		/* Restore environment */
299	lwz	r0,_MSR(r1)
300	mtspr	SRR0,r2
301	mtspr	SRR1,r0
302	lwz	r0,GPR0(r1)
303	lwz	r2,GPR2(r1)
304	lwz	r1,GPR1(r1)
305	SYNC
306	rfi
307
308	.globl get_pvr
309get_pvr:
310	mfspr	r3, PVR
311	blr
312
313/*------------------------------------------------------------------------------*/
314
315/*
316 * void relocate_code (addr_sp, gd, addr_moni)
317 *
318 * This "function" does not return, instead it continues in RAM
319 * after relocating the monitor code.
320 *
321 * r3 = dest
322 * r4 = src
323 * r5 = length in bytes
324 * r6 = cachelinesize
325 */
326	.globl	relocate_code
327relocate_code:
328	mr	r1,  r3		/* Set new stack pointer		*/
329	mr	r9,  r4		/* Save copy of Global Data pointer	*/
330	mr	r10, r5		/* Save copy of Destination Address	*/
331
332	GET_GOT
333	mr	r3,  r5				/* Destination Address	*/
334	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
335	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
336	lwz	r5, GOT(__init_end)
337	sub	r5, r5, r4
338	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
339
340	/*
341	 * Fix GOT pointer:
342	 *
343	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
344	 *
345	 * Offset:
346	 */
347	sub	r15, r10, r4
348
349	/* First our own GOT */
350	add	r12, r12, r15
351	/* then the one used by the C code */
352	add	r30, r30, r15
353
354	/*
355	 * Now relocate code
356	 */
357
358	cmplw	cr1,r3,r4
359	addi	r0,r5,3
360	srwi.	r0,r0,2
361	beq	cr1,4f		/* In place copy is not necessary	*/
362	beq	7f		/* Protect against 0 count		*/
363	mtctr	r0
364	bge	cr1,2f
365
366	la	r8,-4(r4)
367	la	r7,-4(r3)
3681:	lwzu	r0,4(r8)
369	stwu	r0,4(r7)
370	bdnz	1b
371	b	4f
372
3732:	slwi	r0,r0,2
374	add	r8,r4,r0
375	add	r7,r3,r0
3763:	lwzu	r0,-4(r8)
377	stwu	r0,-4(r7)
378	bdnz	3b
379
380/*
381 * Now flush the cache: note that we must start from a cache aligned
382 * address. Otherwise we might miss one cache line.
383 */
3844:	cmpwi	r6,0
385	add	r5,r3,r5
386	beq	7f		/* Always flush prefetch queue in any case */
387	subi	r0,r6,1
388	andc	r3,r3,r0
389	mr	r4,r3
3905:	dcbst	0,r4
391	add	r4,r4,r6
392	cmplw	r4,r5
393	blt	5b
394	sync			/* Wait for all dcbst to complete on bus */
395	mr	r4,r3
3966:	icbi	0,r4
397	add	r4,r4,r6
398	cmplw	r4,r5
399	blt	6b
4007:	sync			/* Wait for all icbi to complete on bus	*/
401	isync
402
403/*
404 * We are done. Do not return, instead branch to second part of board
405 * initialization, now running from RAM.
406 */
407
408	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
409	mtlr	r0
410	blr
411
412in_ram:
413
414	/*
415	 * Relocation Function, r12 point to got2+0x8000
416	 *
417	 * Adjust got2 pointers, no need to check for 0, this code
418	 * already puts a few entries in the table.
419	 */
420	li	r0,__got2_entries@sectoff@l
421	la	r3,GOT(_GOT2_TABLE_)
422	lwz	r11,GOT(_GOT2_TABLE_)
423	mtctr	r0
424	sub	r11,r3,r11
425	addi	r3,r3,-4
4261:	lwzu	r0,4(r3)
427	cmpwi	r0,0
428	beq-	2f
429	add	r0,r0,r11
430	stw	r0,0(r3)
4312:	bdnz	1b
432
433	/*
434	 * Now adjust the fixups and the pointers to the fixups
435	 * in case we need to move ourselves again.
436	 */
437	li	r0,__fixup_entries@sectoff@l
438	lwz	r3,GOT(_FIXUP_TABLE_)
439	cmpwi	r0,0
440	mtctr	r0
441	addi	r3,r3,-4
442	beq	4f
4433:	lwzu	r4,4(r3)
444	lwzux	r0,r4,r11
445	cmpwi	r0,0
446	add	r0,r0,r11
447	stw	r4,0(r3)
448	beq-	5f
449	stw	r0,0(r4)
4505:	bdnz	3b
4514:
452clear_bss:
453	/*
454	 * Now clear BSS segment
455	 */
456	lwz	r3,GOT(__bss_start)
457	lwz	r4,GOT(__bss_end)
458
459	cmplw	0, r3, r4
460	beq	6f
461
462	li	r0, 0
4635:
464	stw	r0, 0(r3)
465	addi	r3, r3, 4
466	cmplw	0, r3, r4
467	bne	5b
4686:
469
470	mr	r3, r9		/* Global Data pointer		*/
471	mr	r4, r10		/* Destination Address		*/
472	bl	board_init_r
473
474	/*
475	 * Copy exception vector code to low memory
476	 *
477	 * r3: dest_addr
478	 * r7: source address, r8: end address, r9: target address
479	 */
480	.globl	trap_init
481trap_init:
482	mflr	r4			/* save link register		*/
483	GET_GOT
484	lwz	r7, GOT(_start)
485	lwz	r8, GOT(_end_of_vectors)
486
487	li	r9, 0x100		/* reset vector always at 0x100 */
488
489	cmplw	0, r7, r8
490	bgelr				/* return if r7>=r8 - just in case */
4911:
492	lwz	r0, 0(r7)
493	stw	r0, 0(r9)
494	addi	r7, r7, 4
495	addi	r9, r9, 4
496	cmplw	0, r7, r8
497	bne	1b
498
499	/*
500	 * relocate `hdlr' and `int_return' entries
501	 */
502	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
503	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
5042:
505	bl	trap_reloc
506	addi	r7, r7, 0x100		/* next exception vector	*/
507	cmplw	0, r7, r8
508	blt	2b
509
510	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
511	bl	trap_reloc
512
513	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
514	bl	trap_reloc
515
516	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
517	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
5183:
519	bl	trap_reloc
520	addi	r7, r7, 0x100		/* next exception vector	*/
521	cmplw	0, r7, r8
522	blt	3b
523
524	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
525	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
5264:
527	bl	trap_reloc
528	addi	r7, r7, 0x100		/* next exception vector	*/
529	cmplw	0, r7, r8
530	blt	4b
531
532	mtlr	r4			/* restore link register	*/
533	blr
534