xref: /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/start.S (revision 14d0a02a168b36e87665b8d7f42fa3e88263d26d) 
1/*
2 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
3 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*  U-Boot - Startup Code for PowerPC based Embedded Boards
26 *
27 *
28 *  The processor starts at 0x00000100 and the code is executed
29 *  from flash. The code is organized to be at an other address
30 *  in memory, but as long we don't jump around before relocating,
31 *  board_init lies at a quite high address and when the cpu has
32 *  jumped there, everything is ok.
33 *  This works because the cpu gives the FLASH (CS0) the whole
34 *  address space at startup, and board_init lies as a echo of
35 *  the flash somewhere up there in the memory map.
36 *
37 *  board_init will change CS0 to be positioned at the correct
38 *  address and (s)dram will be positioned at address 0
39 */
40#include <config.h>
41#include <mpc8xx.h>
42#include <timestamp.h>
43#include <version.h>
44
45#define CONFIG_8xx 1		/* needed for Linux kernel header files */
46#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
47
48#include <ppc_asm.tmpl>
49#include <ppc_defs.h>
50
51#include <asm/cache.h>
52#include <asm/mmu.h>
53
54#ifndef  CONFIG_IDENT_STRING
55#define  CONFIG_IDENT_STRING ""
56#endif
57
58/* We don't want the  MMU yet.
59*/
60#undef	MSR_KERNEL
61#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
62
63/*
64 * Set up GOT: Global Offset Table
65 *
66 * Use r12 to access the GOT
67 */
68	START_GOT
69	GOT_ENTRY(_GOT2_TABLE_)
70	GOT_ENTRY(_FIXUP_TABLE_)
71
72	GOT_ENTRY(_start)
73	GOT_ENTRY(_start_of_vectors)
74	GOT_ENTRY(_end_of_vectors)
75	GOT_ENTRY(transfer_to_handler)
76
77	GOT_ENTRY(__init_end)
78	GOT_ENTRY(_end)
79	GOT_ENTRY(__bss_start)
80	END_GOT
81
82/*
83 * r3 - 1st arg to board_init(): IMMP pointer
84 * r4 - 2nd arg to board_init(): boot flag
85 */
86	.text
87	.long	0x27051956		/* U-Boot Magic Number			*/
88	.globl	version_string
89version_string:
90	.ascii U_BOOT_VERSION
91	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
92	.ascii CONFIG_IDENT_STRING, "\0"
93
94	. = EXC_OFF_SYS_RESET
95	.globl	_start
96_start:
97	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
98	mtspr	638, r3
99
100	/* Initialize machine status; enable machine check interrupt		*/
101	/*----------------------------------------------------------------------*/
102	li	r3, MSR_KERNEL		/* Set ME, RI flags */
103	mtmsr	r3
104	mtspr	SRR1, r3		/* Make SRR1 match MSR */
105
106	mfspr	r3, ICR			/* clear Interrupt Cause Register */
107
108	/* Initialize debug port registers					*/
109	/*----------------------------------------------------------------------*/
110	xor	r0, r0, r0		/* Clear R0 */
111	mtspr	LCTRL1, r0		/* Initialize debug port regs */
112	mtspr	LCTRL2, r0
113	mtspr	COUNTA, r0
114	mtspr	COUNTB, r0
115
116	/* Reset the caches							*/
117	/*----------------------------------------------------------------------*/
118
119	mfspr	r3, IC_CST		/* Clear error bits */
120	mfspr	r3, DC_CST
121
122	lis	r3, IDC_UNALL@h		/* Unlock all */
123	mtspr	IC_CST, r3
124	mtspr	DC_CST, r3
125
126	lis	r3, IDC_INVALL@h	/* Invalidate all */
127	mtspr	IC_CST, r3
128	mtspr	DC_CST, r3
129
130	lis	r3, IDC_DISABLE@h	/* Disable data cache */
131	mtspr	DC_CST, r3
132
133#if !defined(CONFIG_SYS_DELAYED_ICACHE)
134					/* On IP860 and PCU E,
135					 * we cannot enable IC yet
136					 */
137	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
138#endif
139	mtspr	IC_CST, r3
140
141	/* invalidate all tlb's							*/
142	/*----------------------------------------------------------------------*/
143
144	tlbia
145	isync
146
147	/*
148	 * Calculate absolute address in FLASH and jump there
149	 *----------------------------------------------------------------------*/
150
151	lis	r3, CONFIG_SYS_MONITOR_BASE@h
152	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
153	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
154	mtlr	r3
155	blr
156
157in_flash:
158
159	/* initialize some SPRs that are hard to access from C			*/
160	/*----------------------------------------------------------------------*/
161
162	lis	r3, CONFIG_SYS_IMMR@h		/* pass IMMR as arg1 to C routine */
163	ori	r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
164	/* Note: R0 is still 0 here */
165	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
166	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
167
168	/*
169	 * Disable serialized ifetch and show cycles
170	 * (i.e. set processor to normal mode).
171	 * This is also a silicon bug workaround, see errata
172	 */
173
174	li	r2, 0x0007
175	mtspr	ICTRL, r2
176
177	/* Set up debug mode entry */
178
179	lis	r2, CONFIG_SYS_DER@h
180	ori	r2, r2, CONFIG_SYS_DER@l
181	mtspr	DER, r2
182
183	/* let the C-code set up the rest					*/
184	/*									*/
185	/* Be careful to keep code relocatable !				*/
186	/*----------------------------------------------------------------------*/
187
188	GET_GOT			/* initialize GOT access			*/
189
190	/* r3: IMMR */
191	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
192
193	bl	board_init_f	/* run 1st part of board init code (from Flash) */
194
195	/* NOTREACHED - board_init_f() does not return */
196
197
198	.globl	_start_of_vectors
199_start_of_vectors:
200
201/* Machine check */
202	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
203
204/* Data Storage exception.  "Never" generated on the 860. */
205	STD_EXCEPTION(0x300, DataStorage, UnknownException)
206
207/* Instruction Storage exception.  "Never" generated on the 860. */
208	STD_EXCEPTION(0x400, InstStorage, UnknownException)
209
210/* External Interrupt exception. */
211	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
212
213/* Alignment exception. */
214	. = 0x600
215Alignment:
216	EXCEPTION_PROLOG(SRR0, SRR1)
217	mfspr	r4,DAR
218	stw	r4,_DAR(r21)
219	mfspr	r5,DSISR
220	stw	r5,_DSISR(r21)
221	addi	r3,r1,STACK_FRAME_OVERHEAD
222	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
223
224/* Program check exception */
225	. = 0x700
226ProgramCheck:
227	EXCEPTION_PROLOG(SRR0, SRR1)
228	addi	r3,r1,STACK_FRAME_OVERHEAD
229	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
230		MSR_KERNEL, COPY_EE)
231
232	/* No FPU on MPC8xx.  This exception is not supposed to happen.
233	*/
234	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
235
236	/* I guess we could implement decrementer, and may have
237	 * to someday for timekeeping.
238	 */
239	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
240	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
241	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
242	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
243	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
244
245	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
246	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
247
248	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
249	 * for all unimplemented and illegal instructions.
250	 */
251	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
252
253	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
254	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
255	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
256	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
257
258	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
259	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
260	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
261	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
262	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
263	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
264	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
265
266	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
267	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
268	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
269	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
270
271
272	.globl	_end_of_vectors
273_end_of_vectors:
274
275
276	. = 0x2000
277
278/*
279 * This code finishes saving the registers to the exception frame
280 * and jumps to the appropriate handler for the exception.
281 * Register r21 is pointer into trap frame, r1 has new stack pointer.
282 */
283	.globl	transfer_to_handler
284transfer_to_handler:
285	stw	r22,_NIP(r21)
286	lis	r22,MSR_POW@h
287	andc	r23,r23,r22
288	stw	r23,_MSR(r21)
289	SAVE_GPR(7, r21)
290	SAVE_4GPRS(8, r21)
291	SAVE_8GPRS(12, r21)
292	SAVE_8GPRS(24, r21)
293	mflr	r23
294	andi.	r24,r23,0x3f00		/* get vector offset */
295	stw	r24,TRAP(r21)
296	li	r22,0
297	stw	r22,RESULT(r21)
298	mtspr	SPRG2,r22		/* r1 is now kernel sp */
299	lwz	r24,0(r23)		/* virtual address of handler */
300	lwz	r23,4(r23)		/* where to go when done */
301	mtspr	SRR0,r24
302	mtspr	SRR1,r20
303	mtlr	r23
304	SYNC
305	rfi				/* jump to handler, enable MMU */
306
307int_return:
308	mfmsr	r28			/* Disable interrupts */
309	li	r4,0
310	ori	r4,r4,MSR_EE
311	andc	r28,r28,r4
312	SYNC				/* Some chip revs need this... */
313	mtmsr	r28
314	SYNC
315	lwz	r2,_CTR(r1)
316	lwz	r0,_LINK(r1)
317	mtctr	r2
318	mtlr	r0
319	lwz	r2,_XER(r1)
320	lwz	r0,_CCR(r1)
321	mtspr	XER,r2
322	mtcrf	0xFF,r0
323	REST_10GPRS(3, r1)
324	REST_10GPRS(13, r1)
325	REST_8GPRS(23, r1)
326	REST_GPR(31, r1)
327	lwz	r2,_NIP(r1)		/* Restore environment */
328	lwz	r0,_MSR(r1)
329	mtspr	SRR0,r2
330	mtspr	SRR1,r0
331	lwz	r0,GPR0(r1)
332	lwz	r2,GPR2(r1)
333	lwz	r1,GPR1(r1)
334	SYNC
335	rfi
336
337/* Cache functions.
338*/
339	.globl	icache_enable
340icache_enable:
341	SYNC
342	lis	r3, IDC_INVALL@h
343	mtspr	IC_CST, r3
344	lis	r3, IDC_ENABLE@h
345	mtspr	IC_CST, r3
346	blr
347
348	.globl	icache_disable
349icache_disable:
350	SYNC
351	lis	r3, IDC_DISABLE@h
352	mtspr	IC_CST, r3
353	blr
354
355	.globl	icache_status
356icache_status:
357	mfspr	r3, IC_CST
358	srwi	r3, r3, 31	/* >>31 => select bit 0 */
359	blr
360
361	.globl	dcache_enable
362dcache_enable:
363#if 0
364	SYNC
365#endif
366#if 1
367	lis	r3, 0x0400		/* Set cache mode with MMU off */
368	mtspr	MD_CTR, r3
369#endif
370
371	lis	r3, IDC_INVALL@h
372	mtspr	DC_CST, r3
373#if 0
374	lis	r3, DC_SFWT@h
375	mtspr	DC_CST, r3
376#endif
377	lis	r3, IDC_ENABLE@h
378	mtspr	DC_CST, r3
379	blr
380
381	.globl	dcache_disable
382dcache_disable:
383	SYNC
384	lis	r3, IDC_DISABLE@h
385	mtspr	DC_CST, r3
386	lis	r3, IDC_INVALL@h
387	mtspr	DC_CST, r3
388	blr
389
390	.globl	dcache_status
391dcache_status:
392	mfspr	r3, DC_CST
393	srwi	r3, r3, 31	/* >>31 => select bit 0 */
394	blr
395
396	.globl	dc_read
397dc_read:
398	mtspr	DC_ADR, r3
399	mfspr	r3, DC_DAT
400	blr
401
402/*
403 * unsigned int get_immr (unsigned int mask)
404 *
405 * return (mask ? (IMMR & mask) : IMMR);
406 */
407	.globl	get_immr
408get_immr:
409	mr	r4,r3		/* save mask */
410	mfspr	r3, IMMR	/* IMMR */
411	cmpwi	0,r4,0		/* mask != 0 ? */
412	beq	4f
413	and	r3,r3,r4	/* IMMR & mask */
4144:
415	blr
416
417	.globl get_pvr
418get_pvr:
419	mfspr	r3, PVR
420	blr
421
422
423	.globl wr_ic_cst
424wr_ic_cst:
425	mtspr	IC_CST, r3
426	blr
427
428	.globl rd_ic_cst
429rd_ic_cst:
430	mfspr	r3, IC_CST
431	blr
432
433	.globl wr_ic_adr
434wr_ic_adr:
435	mtspr	IC_ADR, r3
436	blr
437
438
439	.globl wr_dc_cst
440wr_dc_cst:
441	mtspr	DC_CST, r3
442	blr
443
444	.globl rd_dc_cst
445rd_dc_cst:
446	mfspr	r3, DC_CST
447	blr
448
449	.globl wr_dc_adr
450wr_dc_adr:
451	mtspr	DC_ADR, r3
452	blr
453
454/*------------------------------------------------------------------------------*/
455
456/*
457 * void relocate_code (addr_sp, gd, addr_moni)
458 *
459 * This "function" does not return, instead it continues in RAM
460 * after relocating the monitor code.
461 *
462 * r3 = dest
463 * r4 = src
464 * r5 = length in bytes
465 * r6 = cachelinesize
466 */
467	.globl	relocate_code
468relocate_code:
469	mr	r1,  r3		/* Set new stack pointer		*/
470	mr	r9,  r4		/* Save copy of Global Data pointer	*/
471	mr	r10, r5		/* Save copy of Destination Address	*/
472
473	GET_GOT
474	mr	r3,  r5				/* Destination Address	*/
475	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
476	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
477	lwz	r5, GOT(__init_end)
478	sub	r5, r5, r4
479	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
480
481	/*
482	 * Fix GOT pointer:
483	 *
484	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
485	 *
486	 * Offset:
487	 */
488	sub	r15, r10, r4
489
490	/* First our own GOT */
491	add	r12, r12, r15
492	/* then the one used by the C code */
493	add	r30, r30, r15
494
495	/*
496	 * Now relocate code
497	 */
498
499	cmplw	cr1,r3,r4
500	addi	r0,r5,3
501	srwi.	r0,r0,2
502	beq	cr1,4f		/* In place copy is not necessary	*/
503	beq	7f		/* Protect against 0 count		*/
504	mtctr	r0
505	bge	cr1,2f
506
507	la	r8,-4(r4)
508	la	r7,-4(r3)
5091:	lwzu	r0,4(r8)
510	stwu	r0,4(r7)
511	bdnz	1b
512	b	4f
513
5142:	slwi	r0,r0,2
515	add	r8,r4,r0
516	add	r7,r3,r0
5173:	lwzu	r0,-4(r8)
518	stwu	r0,-4(r7)
519	bdnz	3b
520
521/*
522 * Now flush the cache: note that we must start from a cache aligned
523 * address. Otherwise we might miss one cache line.
524 */
5254:	cmpwi	r6,0
526	add	r5,r3,r5
527	beq	7f		/* Always flush prefetch queue in any case */
528	subi	r0,r6,1
529	andc	r3,r3,r0
530	mr	r4,r3
5315:	dcbst	0,r4
532	add	r4,r4,r6
533	cmplw	r4,r5
534	blt	5b
535	sync			/* Wait for all dcbst to complete on bus */
536	mr	r4,r3
5376:	icbi	0,r4
538	add	r4,r4,r6
539	cmplw	r4,r5
540	blt	6b
5417:	sync			/* Wait for all icbi to complete on bus	*/
542	isync
543
544/*
545 * We are done. Do not return, instead branch to second part of board
546 * initialization, now running from RAM.
547 */
548
549	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
550	mtlr	r0
551	blr
552
553in_ram:
554
555	/*
556	 * Relocation Function, r12 point to got2+0x8000
557	 *
558	 * Adjust got2 pointers, no need to check for 0, this code
559	 * already puts a few entries in the table.
560	 */
561	li	r0,__got2_entries@sectoff@l
562	la	r3,GOT(_GOT2_TABLE_)
563	lwz	r11,GOT(_GOT2_TABLE_)
564	mtctr	r0
565	sub	r11,r3,r11
566	addi	r3,r3,-4
5671:	lwzu	r0,4(r3)
568	cmpwi	r0,0
569	beq-	2f
570	add	r0,r0,r11
571	stw	r0,0(r3)
5722:	bdnz	1b
573
574	/*
575	 * Now adjust the fixups and the pointers to the fixups
576	 * in case we need to move ourselves again.
577	 */
578	li	r0,__fixup_entries@sectoff@l
579	lwz	r3,GOT(_FIXUP_TABLE_)
580	cmpwi	r0,0
581	mtctr	r0
582	addi	r3,r3,-4
583	beq	4f
5843:	lwzu	r4,4(r3)
585	lwzux	r0,r4,r11
586	add	r0,r0,r11
587	stw	r10,0(r3)
588	stw	r0,0(r4)
589	bdnz	3b
5904:
591clear_bss:
592	/*
593	 * Now clear BSS segment
594	 */
595	lwz	r3,GOT(__bss_start)
596	lwz	r4,GOT(_end)
597
598	cmplw	0, r3, r4
599	beq	6f
600
601	li	r0, 0
6025:
603	stw	r0, 0(r3)
604	addi	r3, r3, 4
605	cmplw	0, r3, r4
606	bne	5b
6076:
608
609	mr	r3, r9		/* Global Data pointer		*/
610	mr	r4, r10		/* Destination Address		*/
611	bl	board_init_r
612
613	/*
614	 * Copy exception vector code to low memory
615	 *
616	 * r3: dest_addr
617	 * r7: source address, r8: end address, r9: target address
618	 */
619	.globl	trap_init
620trap_init:
621	mflr	r4			/* save link register		*/
622	GET_GOT
623	lwz	r7, GOT(_start)
624	lwz	r8, GOT(_end_of_vectors)
625
626	li	r9, 0x100		/* reset vector always at 0x100 */
627
628	cmplw	0, r7, r8
629	bgelr				/* return if r7>=r8 - just in case */
6301:
631	lwz	r0, 0(r7)
632	stw	r0, 0(r9)
633	addi	r7, r7, 4
634	addi	r9, r9, 4
635	cmplw	0, r7, r8
636	bne	1b
637
638	/*
639	 * relocate `hdlr' and `int_return' entries
640	 */
641	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
642	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
6432:
644	bl	trap_reloc
645	addi	r7, r7, 0x100		/* next exception vector	*/
646	cmplw	0, r7, r8
647	blt	2b
648
649	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
650	bl	trap_reloc
651
652	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
653	bl	trap_reloc
654
655	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
656	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
6573:
658	bl	trap_reloc
659	addi	r7, r7, 0x100		/* next exception vector	*/
660	cmplw	0, r7, r8
661	blt	3b
662
663	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
664	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
6654:
666	bl	trap_reloc
667	addi	r7, r7, 0x100		/* next exception vector	*/
668	cmplw	0, r7, r8
669	blt	4b
670
671	mtlr	r4			/* restore link register	*/
672	blr
673