1 /* 2 * (C) Copyright 2000-2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <watchdog.h> 10 11 #include <mpc8xx.h> 12 #include <commproc.h> 13 14 #if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS) 15 DECLARE_GLOBAL_DATA_PTR; 16 #endif 17 18 #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ 19 defined(CONFIG_SYS_SMC_UCODE_PATCH) 20 void cpm_load_patch (volatile immap_t * immr); 21 #endif 22 23 /* 24 * Breath some life into the CPU... 25 * 26 * Set up the memory map, 27 * initialize a bunch of registers, 28 * initialize the UPM's 29 */ 30 void cpu_init_f (volatile immap_t * immr) 31 { 32 volatile memctl8xx_t *memctl = &immr->im_memctl; 33 # ifdef CONFIG_SYS_PLPRCR 34 ulong mfmask; 35 # endif 36 ulong reg; 37 38 /* SYPCR - contains watchdog control (11-9) */ 39 40 immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR; 41 42 #if defined(CONFIG_WATCHDOG) 43 reset_8xx_watchdog (immr); 44 #endif /* CONFIG_WATCHDOG */ 45 46 /* SIUMCR - contains debug pin configuration (11-6) */ 47 #ifndef CONFIG_SVM_SC8xx 48 immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; 49 #else 50 immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR; 51 #endif 52 /* initialize timebase status and control register (11-26) */ 53 /* unlock TBSCRK */ 54 55 immr->im_sitk.sitk_tbscrk = KAPWR_KEY; 56 immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR; 57 58 /* initialize the PIT (11-31) */ 59 60 immr->im_sitk.sitk_piscrk = KAPWR_KEY; 61 immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; 62 63 /* System integration timers. Don't change EBDF! (15-27) */ 64 65 immr->im_clkrstk.cark_sccrk = KAPWR_KEY; 66 reg = immr->im_clkrst.car_sccr; 67 reg &= SCCR_MASK; 68 reg |= CONFIG_SYS_SCCR; 69 immr->im_clkrst.car_sccr = reg; 70 71 /* PLL (CPU clock) settings (15-30) */ 72 73 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; 74 75 /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to 76 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, 77 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF 78 * field value. 79 * 80 * For newer (starting MPC866) chips PLPRCR layout is different. 81 */ 82 #ifdef CONFIG_SYS_PLPRCR 83 if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK) 84 mfmask = PLPRCR_MFACT_MSK; 85 else 86 mfmask = PLPRCR_MF_MSK; 87 88 if ((CONFIG_SYS_PLPRCR & mfmask) != 0) 89 reg = CONFIG_SYS_PLPRCR; /* reset control bits */ 90 else { 91 reg = immr->im_clkrst.car_plprcr; 92 reg &= mfmask; /* isolate MF-related fields */ 93 reg |= CONFIG_SYS_PLPRCR; /* reset control bits */ 94 } 95 immr->im_clkrst.car_plprcr = reg; 96 #endif 97 98 /* 99 * Memory Controller: 100 */ 101 102 /* perform BR0 reset that MPC850 Rev. A can't guarantee */ 103 reg = memctl->memc_br0; 104 reg &= BR_PS_MSK; /* Clear everything except Port Size bits */ 105 reg |= BR_V; /* then add just the "Bank Valid" bit */ 106 memctl->memc_br0 = reg; 107 108 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at 109 * preliminary addresses - these have to be modified later 110 * when FLASH size has been determined 111 * 112 * Depending on the size of the memory region defined by 113 * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the 114 * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't 115 * map CONFIG_SYS_MONITOR_BASE. 116 * 117 * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is 118 * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000. 119 * 120 * If BR0 wasn't loaded with address base 0xff000000, then BR0's 121 * base address remains as 0x00000000. However, the address mask 122 * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped 123 * into the Bank0. 124 * 125 * This is why CONFIG_IVMS8 and similar boards must load BR0 with 126 * CONFIG_SYS_BR0_PRELIM in advance. 127 * 128 * [Thanks to Michael Liao for this explanation. 129 * I owe him a free beer. - wd] 130 */ 131 132 #if defined(CONFIG_HERMES) || \ 133 defined(CONFIG_ICU862) || \ 134 defined(CONFIG_IP860) || \ 135 defined(CONFIG_IVML24) || \ 136 defined(CONFIG_IVMS8) || \ 137 defined(CONFIG_LWMON) || \ 138 defined(CONFIG_MHPC) || \ 139 defined(CONFIG_R360MPI) || \ 140 defined(CONFIG_RMU) || \ 141 defined(CONFIG_SPD823TS) 142 143 memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; 144 #endif 145 146 #if defined(CONFIG_SYS_OR0_REMAP) 147 memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; 148 #endif 149 #if defined(CONFIG_SYS_OR1_REMAP) 150 memctl->memc_or1 = CONFIG_SYS_OR1_REMAP; 151 #endif 152 #if defined(CONFIG_SYS_OR5_REMAP) 153 memctl->memc_or5 = CONFIG_SYS_OR5_REMAP; 154 #endif 155 156 /* now restrict to preliminary range */ 157 memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; 158 memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; 159 160 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) 161 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; 162 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; 163 #endif 164 165 #if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */ 166 memctl->memc_br0 = 0; 167 #endif 168 169 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 170 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; 171 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; 172 #endif 173 174 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) 175 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; 176 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; 177 #endif 178 179 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) 180 memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; 181 memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; 182 #endif 183 184 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) 185 memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; 186 memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; 187 #endif 188 189 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) 190 memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM; 191 memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM; 192 #endif 193 194 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) 195 memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM; 196 memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; 197 #endif 198 199 /* 200 * Reset CPM 201 */ 202 immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG; 203 do { /* Spin until command processed */ 204 __asm__ ("eieio"); 205 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); 206 207 #ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */ 208 /* write config value */ 209 immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; 210 #endif 211 212 #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ 213 defined(CONFIG_SYS_SMC_UCODE_PATCH) 214 cpm_load_patch (immr); /* load mpc8xx microcode patch */ 215 #endif 216 } 217 218 /* 219 * initialize higher level parts of CPU like timers 220 */ 221 int cpu_init_r (void) 222 { 223 #if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS) 224 bd_t *bd = gd->bd; 225 volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base); 226 #endif 227 228 #ifdef CONFIG_SYS_RTCSC 229 /* Unlock RTSC register */ 230 immr->im_sitk.sitk_rtcsck = KAPWR_KEY; 231 /* write config value */ 232 immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC; 233 #endif 234 235 #ifdef CONFIG_SYS_RMDS 236 /* write config value */ 237 immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS; 238 #endif 239 return (0); 240 } 241