1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2af042474SKumar Gala /*
3af042474SKumar Gala * Copyright 2010 Freescale Semiconductor, Inc.
4af042474SKumar Gala */
5af042474SKumar Gala
6af042474SKumar Gala #include <config.h>
7af042474SKumar Gala #include <common.h>
8af042474SKumar Gala #include <asm/io.h>
9af042474SKumar Gala #include <asm/immap_86xx.h>
10af042474SKumar Gala #include <asm/fsl_serdes.h>
11af042474SKumar Gala
12af042474SKumar Gala #define SRDS1_MAX_LANES 4
13af042474SKumar Gala #define SRDS2_MAX_LANES 4
14af042474SKumar Gala
15af042474SKumar Gala static u32 serdes1_prtcl_map, serdes2_prtcl_map;
16af042474SKumar Gala
17af042474SKumar Gala static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
18af042474SKumar Gala [0x1] = {PCIE1, PCIE1, PCIE1, PCIE1},
19af042474SKumar Gala [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1},
20af042474SKumar Gala [0x7] = {NONE, NONE, NONE, NONE},
21af042474SKumar Gala };
22af042474SKumar Gala
23af042474SKumar Gala static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
24af042474SKumar Gala [0x0] = {PCIE2, PCIE2, PCIE2, PCIE2},
25af042474SKumar Gala [0x4] = {PCIE2, PCIE2, PCIE2, PCIE2},
26af042474SKumar Gala [0x7] = {NONE, NONE, NONE, NONE},
27af042474SKumar Gala };
28af042474SKumar Gala
is_serdes_configured(enum srds_prtcl device)29af042474SKumar Gala int is_serdes_configured(enum srds_prtcl device)
30af042474SKumar Gala {
3171fe2225SHou Zhiqiang int ret;
3271fe2225SHou Zhiqiang
3371fe2225SHou Zhiqiang if (!(serdes1_prtcl_map & (1 << NONE)))
3471fe2225SHou Zhiqiang fsl_serdes_init();
3571fe2225SHou Zhiqiang
3671fe2225SHou Zhiqiang ret = (1 << device) & serdes1_prtcl_map;
37af042474SKumar Gala
38af042474SKumar Gala if (ret)
39af042474SKumar Gala return ret;
40af042474SKumar Gala
4171fe2225SHou Zhiqiang if (!(serdes2_prtcl_map & (1 << NONE)))
4271fe2225SHou Zhiqiang fsl_serdes_init();
4371fe2225SHou Zhiqiang
44af042474SKumar Gala return (1 << device) & serdes2_prtcl_map;
45af042474SKumar Gala }
46af042474SKumar Gala
fsl_serdes_init(void)47af042474SKumar Gala void fsl_serdes_init(void)
48af042474SKumar Gala {
49af042474SKumar Gala immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
50af042474SKumar Gala ccsr_gur_t *gur = &immap->im_gur;
51af042474SKumar Gala u32 pordevsr = in_be32(&gur->pordevsr);
52af042474SKumar Gala u32 srds_cfg = (pordevsr & MPC8610_PORDEVSR_IO_SEL) >>
53af042474SKumar Gala MPC8610_PORDEVSR_IO_SEL_SHIFT;
54af042474SKumar Gala int lane;
55af042474SKumar Gala
5671fe2225SHou Zhiqiang if (serdes1_prtcl_map & (1 << NONE) &&
5771fe2225SHou Zhiqiang serdes2_prtcl_map & (1 << NONE))
5871fe2225SHou Zhiqiang return;
5971fe2225SHou Zhiqiang
60af042474SKumar Gala debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
61af042474SKumar Gala
62e51e47d3SAxel Lin if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
63af042474SKumar Gala printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
64af042474SKumar Gala return;
65af042474SKumar Gala }
66af042474SKumar Gala for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
67af042474SKumar Gala enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
68af042474SKumar Gala serdes1_prtcl_map |= (1 << lane_prtcl);
69af042474SKumar Gala }
70af042474SKumar Gala
7171fe2225SHou Zhiqiang /* Set the first bit to indicate serdes has been initialized */
7271fe2225SHou Zhiqiang serdes1_prtcl_map |= (1 << NONE);
7371fe2225SHou Zhiqiang
74e51e47d3SAxel Lin if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
75af042474SKumar Gala printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
76af042474SKumar Gala return;
77af042474SKumar Gala }
78af042474SKumar Gala
79af042474SKumar Gala for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
80af042474SKumar Gala enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
81af042474SKumar Gala serdes2_prtcl_map |= (1 << lane_prtcl);
82af042474SKumar Gala }
8371fe2225SHou Zhiqiang
8471fe2225SHou Zhiqiang /* Set the first bit to indicate serdes has been initialized */
8571fe2225SHou Zhiqiang serdes2_prtcl_map |= (1 << NONE);
86af042474SKumar Gala }
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