1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <ppc_asm.tmpl> 15 #include <linux/compiler.h> 16 #include <asm/processor.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS 23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6 24 #endif 25 /* --------------------------------------------------------------- */ 26 27 void get_sys_info(sys_info_t *sys_info) 28 { 29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 30 #ifdef CONFIG_FSL_IFC 31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 32 u32 ccr; 33 #endif 34 #ifdef CONFIG_FSL_CORENET 35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 36 unsigned int cpu; 37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; 39 #endif 40 41 const u8 core_cplx_PLL[16] = { 42 [ 0] = 0, /* CC1 PPL / 1 */ 43 [ 1] = 0, /* CC1 PPL / 2 */ 44 [ 2] = 0, /* CC1 PPL / 4 */ 45 [ 4] = 1, /* CC2 PPL / 1 */ 46 [ 5] = 1, /* CC2 PPL / 2 */ 47 [ 6] = 1, /* CC2 PPL / 4 */ 48 [ 8] = 2, /* CC3 PPL / 1 */ 49 [ 9] = 2, /* CC3 PPL / 2 */ 50 [10] = 2, /* CC3 PPL / 4 */ 51 [12] = 3, /* CC4 PPL / 1 */ 52 [13] = 3, /* CC4 PPL / 2 */ 53 [14] = 3, /* CC4 PPL / 4 */ 54 }; 55 56 const u8 core_cplx_pll_div[16] = { 57 [ 0] = 1, /* CC1 PPL / 1 */ 58 [ 1] = 2, /* CC1 PPL / 2 */ 59 [ 2] = 4, /* CC1 PPL / 4 */ 60 [ 4] = 1, /* CC2 PPL / 1 */ 61 [ 5] = 2, /* CC2 PPL / 2 */ 62 [ 6] = 4, /* CC2 PPL / 4 */ 63 [ 8] = 1, /* CC3 PPL / 1 */ 64 [ 9] = 2, /* CC3 PPL / 2 */ 65 [10] = 4, /* CC3 PPL / 4 */ 66 [12] = 1, /* CC4 PPL / 1 */ 67 [13] = 2, /* CC4 PPL / 2 */ 68 [14] = 4, /* CC4 PPL / 4 */ 69 }; 70 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; 71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 72 uint rcw_tmp; 73 #endif 74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; 75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 76 uint mem_pll_rat; 77 78 sys_info->freq_systembus = sysclk; 79 #ifdef CONFIG_DDR_CLK_FREQ 80 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; 81 #else 82 sys_info->freq_ddrbus = sysclk; 83 #endif 84 85 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 86 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 87 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 88 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 89 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of 90 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 91 * it uses 6. 92 */ 93 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 94 if (SVR_MAJ(get_svr()) >= 2) 95 mem_pll_rat *= 2; 96 #endif 97 if (mem_pll_rat > 2) 98 sys_info->freq_ddrbus *= mem_pll_rat; 99 else 100 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; 101 102 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { 103 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; 104 if (ratio[i] > 4) 105 freq_c_pll[i] = sysclk * ratio[i]; 106 else 107 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; 108 } 109 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 110 /* 111 * As per CHASSIS2 architeture total 12 clusters are posible and 112 * Each cluster has up to 4 cores, sharing the same PLL selection. 113 * The cluster clock assignment is SoC defined. 114 * 115 * Total 4 clock groups are possible with 3 PLLs each. 116 * as per array indices, clock group A has 0, 1, 2 numbered PLLs & 117 * clock group B has 3, 4, 6 and so on. 118 * 119 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster 120 * depends upon the SoC architeture. Same applies to other 121 * clock groups and clusters. 122 * 123 */ 124 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 125 int cluster = fsl_qoriq_core_to_cluster(cpu); 126 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) 127 & 0xf; 128 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 129 cplx_pll += cc_group[cluster] - 1; 130 sys_info->freq_processor[cpu] = 131 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 132 } 133 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) 134 #define FM1_CLK_SEL 0xe0000000 135 #define FM1_CLK_SHIFT 29 136 #else 137 #define PME_CLK_SEL 0xe0000000 138 #define PME_CLK_SHIFT 29 139 #define FM1_CLK_SEL 0x1c000000 140 #define FM1_CLK_SHIFT 26 141 #endif 142 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 143 rcw_tmp = in_be32(&gur->rcwsr[7]); 144 #endif 145 146 #ifdef CONFIG_SYS_DPAA_PME 147 #ifndef CONFIG_PME_PLAT_CLK_DIV 148 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { 149 case 1: 150 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; 151 break; 152 case 2: 153 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; 154 break; 155 case 3: 156 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; 157 break; 158 case 4: 159 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; 160 break; 161 case 6: 162 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; 163 break; 164 case 7: 165 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; 166 break; 167 default: 168 printf("Error: Unknown PME clock select!\n"); 169 case 0: 170 sys_info->freq_pme = sys_info->freq_systembus / 2; 171 break; 172 173 } 174 #else 175 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; 176 177 #endif 178 #endif 179 180 #ifdef CONFIG_SYS_DPAA_QBMAN 181 sys_info->freq_qman = sys_info->freq_systembus / 2; 182 #endif 183 184 #ifdef CONFIG_SYS_DPAA_FMAN 185 #ifndef CONFIG_FM_PLAT_CLK_DIV 186 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { 187 case 1: 188 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; 189 break; 190 case 2: 191 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; 192 break; 193 case 3: 194 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; 195 break; 196 case 4: 197 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; 198 break; 199 case 5: 200 sys_info->freq_fman[0] = sys_info->freq_systembus; 201 break; 202 case 6: 203 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; 204 break; 205 case 7: 206 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; 207 break; 208 default: 209 printf("Error: Unknown FMan1 clock select!\n"); 210 case 0: 211 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 212 break; 213 } 214 #if (CONFIG_SYS_NUM_FMAN) == 2 215 #ifdef CONFIG_SYS_FM2_CLK 216 #define FM2_CLK_SEL 0x00000038 217 #define FM2_CLK_SHIFT 3 218 rcw_tmp = in_be32(&gur->rcwsr[15]); 219 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { 220 case 1: 221 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; 222 break; 223 case 2: 224 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; 225 break; 226 case 3: 227 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; 228 break; 229 case 4: 230 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; 231 break; 232 case 5: 233 sys_info->freq_fman[1] = sys_info->freq_systembus; 234 break; 235 case 6: 236 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; 237 break; 238 case 7: 239 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; 240 break; 241 default: 242 printf("Error: Unknown FMan2 clock select!\n"); 243 case 0: 244 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 245 break; 246 } 247 #endif 248 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 249 #else 250 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; 251 #endif 252 #endif 253 254 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 255 256 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 257 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) 258 & 0xf; 259 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 260 261 sys_info->freq_processor[cpu] = 262 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 263 } 264 #define PME_CLK_SEL 0x80000000 265 #define FM1_CLK_SEL 0x40000000 266 #define FM2_CLK_SEL 0x20000000 267 #define HWA_ASYNC_DIV 0x04000000 268 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 269 #define HWA_CC_PLL 1 270 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 271 #define HWA_CC_PLL 2 272 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 273 #define HWA_CC_PLL 2 274 #else 275 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 276 #endif 277 rcw_tmp = in_be32(&gur->rcwsr[7]); 278 279 #ifdef CONFIG_SYS_DPAA_PME 280 if (rcw_tmp & PME_CLK_SEL) { 281 if (rcw_tmp & HWA_ASYNC_DIV) 282 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; 283 else 284 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; 285 } else { 286 sys_info->freq_pme = sys_info->freq_systembus / 2; 287 } 288 #endif 289 290 #ifdef CONFIG_SYS_DPAA_FMAN 291 if (rcw_tmp & FM1_CLK_SEL) { 292 if (rcw_tmp & HWA_ASYNC_DIV) 293 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; 294 else 295 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; 296 } else { 297 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 298 } 299 #if (CONFIG_SYS_NUM_FMAN) == 2 300 if (rcw_tmp & FM2_CLK_SEL) { 301 if (rcw_tmp & HWA_ASYNC_DIV) 302 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; 303 else 304 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; 305 } else { 306 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 307 } 308 #endif 309 #endif 310 311 #ifdef CONFIG_SYS_DPAA_QBMAN 312 sys_info->freq_qman = sys_info->freq_systembus / 2; 313 #endif 314 315 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 316 317 #else /* CONFIG_FSL_CORENET */ 318 uint plat_ratio, e500_ratio, half_freq_systembus; 319 int i; 320 #ifdef CONFIG_QE 321 __maybe_unused u32 qe_ratio; 322 #endif 323 324 plat_ratio = (gur->porpllsr) & 0x0000003e; 325 plat_ratio >>= 1; 326 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 327 328 /* Divide before multiply to avoid integer 329 * overflow for processor speeds above 2GHz */ 330 half_freq_systembus = sys_info->freq_systembus/2; 331 for (i = 0; i < cpu_numcores(); i++) { 332 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 333 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; 334 } 335 336 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ 337 sys_info->freq_ddrbus = sys_info->freq_systembus; 338 339 #ifdef CONFIG_DDR_CLK_FREQ 340 { 341 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 342 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 343 if (ddr_ratio != 0x7) 344 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 345 } 346 #endif 347 348 #ifdef CONFIG_QE 349 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 350 sys_info->freq_qe = sys_info->freq_systembus; 351 #else 352 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 353 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 354 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; 355 #endif 356 #endif 357 358 #ifdef CONFIG_SYS_DPAA_FMAN 359 sys_info->freq_fman[0] = sys_info->freq_systembus; 360 #endif 361 362 #endif /* CONFIG_FSL_CORENET */ 363 364 #if defined(CONFIG_FSL_LBC) 365 uint lcrr_div; 366 #if defined(CONFIG_SYS_LBC_LCRR) 367 /* We will program LCRR to this value later */ 368 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 369 #else 370 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 371 #endif 372 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 373 #if defined(CONFIG_FSL_CORENET) 374 /* If this is corenet based SoC, bit-representation 375 * for four times the clock divider values. 376 */ 377 lcrr_div *= 4; 378 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 379 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 380 /* 381 * Yes, the entire PQ38 family use the same 382 * bit-representation for twice the clock divider values. 383 */ 384 lcrr_div *= 2; 385 #endif 386 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; 387 } else { 388 /* In case anyone cares what the unknown value is */ 389 sys_info->freq_localbus = lcrr_div; 390 } 391 #endif 392 393 #if defined(CONFIG_FSL_IFC) 394 ccr = in_be32(&ifc_regs->ifc_ccr); 395 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 396 397 sys_info->freq_localbus = sys_info->freq_systembus / ccr; 398 #endif 399 } 400 401 402 int get_clocks (void) 403 { 404 sys_info_t sys_info; 405 #ifdef CONFIG_MPC8544 406 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 407 #endif 408 #if defined(CONFIG_CPM2) 409 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 410 uint sccr, dfbrg; 411 412 /* set VCO = 4 * BRG */ 413 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 414 sccr = cpm->im_cpm_intctl.sccr; 415 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 416 #endif 417 get_sys_info (&sys_info); 418 gd->cpu_clk = sys_info.freq_processor[0]; 419 gd->bus_clk = sys_info.freq_systembus; 420 gd->mem_clk = sys_info.freq_ddrbus; 421 gd->arch.lbc_clk = sys_info.freq_localbus; 422 423 #ifdef CONFIG_QE 424 gd->arch.qe_clk = sys_info.freq_qe; 425 gd->arch.brg_clk = gd->arch.qe_clk / 2; 426 #endif 427 /* 428 * The base clock for I2C depends on the actual SOC. Unfortunately, 429 * there is no pattern that can be used to determine the frequency, so 430 * the only choice is to look up the actual SOC number and use the value 431 * for that SOC. This information is taken from application note 432 * AN2919. 433 */ 434 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 435 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ 436 defined(CONFIG_P1022) 437 gd->arch.i2c1_clk = sys_info.freq_systembus; 438 #elif defined(CONFIG_MPC8544) 439 /* 440 * On the 8544, the I2C clock is the same as the SEC clock. This can be 441 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 442 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 443 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 444 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 445 */ 446 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 447 gd->arch.i2c1_clk = sys_info.freq_systembus / 3; 448 else 449 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 450 #else 451 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 452 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 453 #endif 454 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 455 456 #if defined(CONFIG_FSL_ESDHC) 457 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 458 defined(CONFIG_P1014) 459 gd->arch.sdhc_clk = gd->bus_clk; 460 #else 461 gd->arch.sdhc_clk = gd->bus_clk / 2; 462 #endif 463 #endif /* defined(CONFIG_FSL_ESDHC) */ 464 465 #if defined(CONFIG_CPM2) 466 gd->arch.vco_out = 2*sys_info.freq_systembus; 467 gd->arch.cpm_clk = gd->arch.vco_out / 2; 468 gd->arch.scc_clk = gd->arch.vco_out / 4; 469 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); 470 #endif 471 472 if(gd->cpu_clk != 0) return (0); 473 else return (1); 474 } 475 476 477 /******************************************** 478 * get_bus_freq 479 * return system bus freq in Hz 480 *********************************************/ 481 ulong get_bus_freq (ulong dummy) 482 { 483 return gd->bus_clk; 484 } 485 486 /******************************************** 487 * get_ddr_freq 488 * return ddr bus freq in Hz 489 *********************************************/ 490 ulong get_ddr_freq (ulong dummy) 491 { 492 return gd->mem_clk; 493 } 494