xref: /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/release.S (revision a2af6a7a84c32ee3c1500000d2a0238052a4f5e1) 
1/*
2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc85xx.h>
27#include <version.h>
28
29#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
30
31#include <ppc_asm.tmpl>
32#include <ppc_defs.h>
33
34#include <asm/cache.h>
35#include <asm/mmu.h>
36
37/* To boot secondary cpus, we need a place for them to start up.
38 * Normally, they start at 0xfffffffc, but that's usually the
39 * firmware, and we don't want to have to run the firmware again.
40 * Instead, the primary cpu will set the BPTR to point here to
41 * this page.  We then set up the core, and head to
42 * start_secondary.  Note that this means that the code below
43 * must never exceed 1023 instructions (the branch at the end
44 * would then be the 1024th).
45 */
46	.globl	__secondary_start_page
47	.align	12
48__secondary_start_page:
49/* First do some preliminary setup */
50	lis	r3, HID0_EMCP@h		/* enable machine check */
51#ifndef CONFIG_E500MC
52	ori	r3,r3,HID0_TBEN@l	/* enable Timebase */
53#endif
54#ifdef CONFIG_PHYS_64BIT
55	ori	r3,r3,HID0_ENMAS7@l	/* enable MAS7 updates */
56#endif
57	mtspr	SPRN_HID0,r3
58
59#ifndef CONFIG_E500MC
60	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
61	mfspr   r0,PVR
62	andi.	r0,r0,0xff
63	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
64	blt 1f
65	/* Set MBDD bit also */
66	ori r3, r3, HID1_MBDD@l
671:
68	mtspr	SPRN_HID1,r3
69#endif
70
71#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
72	mfspr	r3,977
73	oris	r3,r3,0x0100
74	mtspr	977,r3
75#endif
76
77	/* Enable branch prediction */
78	lis	r3,BUCSR_ENABLE@h
79	ori	r3,r3,BUCSR_ENABLE@l
80	mtspr	SPRN_BUCSR,r3
81
82	/* Ensure TB is 0 */
83	li	r3,0
84	mttbl	r3
85	mttbu	r3
86
87	/* Enable/invalidate the I-Cache */
88	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
89	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
90	mtspr	SPRN_L1CSR1,r2
911:
92	mfspr	r3,SPRN_L1CSR1
93	and.	r1,r3,r2
94	bne	1b
95
96	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
97	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
98	mtspr	SPRN_L1CSR1,r3
99	isync
1002:
101	mfspr	r3,SPRN_L1CSR1
102	andi.	r1,r3,L1CSR1_ICE@l
103	beq	2b
104
105	/* Enable/invalidate the D-Cache */
106	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
107	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
108	mtspr	SPRN_L1CSR0,r2
1091:
110	mfspr	r3,SPRN_L1CSR0
111	and.	r1,r3,r2
112	bne	1b
113
114	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
115	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
116	mtspr	SPRN_L1CSR0,r3
117	isync
1182:
119	mfspr	r3,SPRN_L1CSR0
120	andi.	r1,r3,L1CSR0_DCE@l
121	beq	2b
122
123#define toreset(x) (x - __secondary_start_page + 0xfffff000)
124
125	/* get our PIR to figure out our table entry */
126	lis	r3,toreset(__spin_table)@h
127	ori	r3,r3,toreset(__spin_table)@l
128
129	/* r10 has the base address for the entry */
130	mfspr	r0,SPRN_PIR
131#ifdef CONFIG_E500MC
132	rlwinm	r4,r0,27,27,31
133#else
134	mr	r4,r0
135#endif
136	slwi	r8,r4,5
137	add	r10,r3,r8
138
139#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
140	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
141	slwi	r8,r4,1
142	addi	r8,r8,32
143	mtspr	L1CSR2,r8
144#endif
145
146#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
147	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
148	/*
149	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
150	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
151	 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
152	 */
153	mfspr   r3,SPRN_SVR
154	rlwinm	r6,r3,24,~0x800		/* clear E bit */
155
156	lis	r5,SVR_P4080@h
157	ori	r5,r5,SVR_P4080@l
158	cmpw	r6,r5
159	bne	1f
160
161	rlwinm  r3,r3,0,0xf0
162	li      r5,0x30
163	cmpw    r3,r5
164	bge     2f
1651:
166#ifdef	CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
167	lis	r3,toreset(enable_cpu_a011_workaround)@ha
168	lwz	r3,toreset(enable_cpu_a011_workaround)@l(r3)
169	cmpwi	r3,0
170	beq	2f
171#endif
172	mfspr	r3,L1CSR2
173	oris	r3,r3,(L1CSR2_DCWS)@h
174	mtspr	L1CSR2,r3
1752:
176#endif
177
178#ifdef CONFIG_BACKSIDE_L2_CACHE
179	/* skip L2 setup on P2040/P2040E as they have no L2 */
180	mfspr	r3,SPRN_SVR
181	rlwinm	r6,r3,24,~0x800		/* clear E bit of SVR */
182
183	lis	r3,SVR_P2040@h
184	ori	r3,r3,SVR_P2040@l
185	cmpw	r6,r3
186	beq 3f
187
188	/* Enable/invalidate the L2 cache */
189	msync
190	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
191	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
192	mtspr	SPRN_L2CSR0,r2
1931:
194	mfspr	r3,SPRN_L2CSR0
195	and.	r1,r3,r2
196	bne	1b
197
198#ifdef CONFIG_SYS_CACHE_STASHING
199	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
200	addi	r3,r8,1
201	mtspr	SPRN_L2CSR1,r3
202#endif
203
204	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
205	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
206	mtspr	SPRN_L2CSR0,r3
207	isync
2082:
209	mfspr	r3,SPRN_L2CSR0
210	andis.	r1,r3,L2CSR0_L2E@h
211	beq	2b
212#endif
2133:
214
215#define EPAPR_MAGIC		(0x45504150)
216#define ENTRY_ADDR_UPPER	0
217#define ENTRY_ADDR_LOWER	4
218#define ENTRY_R3_UPPER		8
219#define ENTRY_R3_LOWER		12
220#define ENTRY_RESV		16
221#define ENTRY_PIR		20
222#define ENTRY_R6_UPPER		24
223#define ENTRY_R6_LOWER		28
224#define ENTRY_SIZE		32
225
226	/* setup the entry */
227	li	r3,0
228	li	r8,1
229	stw	r0,ENTRY_PIR(r10)
230	stw	r3,ENTRY_ADDR_UPPER(r10)
231	stw	r8,ENTRY_ADDR_LOWER(r10)
232	stw	r3,ENTRY_R3_UPPER(r10)
233	stw	r4,ENTRY_R3_LOWER(r10)
234	stw	r3,ENTRY_R6_UPPER(r10)
235	stw	r3,ENTRY_R6_LOWER(r10)
236
237	/* load r13 with the address of the 'bootpg' in SDRAM */
238	lis	r13,toreset(__bootpg_addr)@h
239	ori	r13,r13,toreset(__bootpg_addr)@l
240	lwz	r13,0(r13)
241
242	/* setup mapping for AS = 1, and jump there */
243	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
244	mtspr	SPRN_MAS0,r11
245	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
246	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
247	mtspr	SPRN_MAS1,r11
248	oris	r11,r13,(MAS2_I|MAS2_G)@h
249	ori	r11,r13,(MAS2_I|MAS2_G)@l
250	mtspr	SPRN_MAS2,r11
251	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
252	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
253	mtspr	SPRN_MAS3,r11
254	tlbwe
255
256	bl	1f
2571:	mflr	r11
258	/*
259	 * OR in 0xfff to create a mask of the bootpg SDRAM address.  We use
260	 * this mask to fixup the cpu spin table and the address that we want
261	 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
262	 * bootpg is at 0x7ffff000 in SDRAM.
263	 */
264	ori	r13,r13,0xfff
265	and	r11, r11, r13
266	and	r10, r10, r13
267
268	addi	r11,r11,(2f-1b)
269	mfmsr	r13
270	ori	r12,r13,MSR_IS|MSR_DS@l
271
272	mtspr	SPRN_SRR0,r11
273	mtspr	SPRN_SRR1,r12
274	rfi
275
276	/* spin waiting for addr */
2772:
278	lwz	r4,ENTRY_ADDR_LOWER(r10)
279	andi.	r11,r4,1
280	bne	2b
281	isync
282
283	/* setup IVORs to match fixed offsets */
284#include "fixed_ivor.S"
285
286	/* get the upper bits of the addr */
287	lwz	r11,ENTRY_ADDR_UPPER(r10)
288
289	/* setup branch addr */
290	mtspr	SPRN_SRR0,r4
291
292	/* mark the entry as released */
293	li	r8,3
294	stw	r8,ENTRY_ADDR_LOWER(r10)
295
296	/* mask by ~64M to setup our tlb we will jump to */
297	rlwinm	r12,r4,0,0,5
298
299	/* setup r3, r4, r5, r6, r7, r8, r9 */
300	lwz	r3,ENTRY_R3_LOWER(r10)
301	li	r4,0
302	li	r5,0
303	lwz	r6,ENTRY_R6_LOWER(r10)
304	lis	r7,(64*1024*1024)@h
305	li	r8,0
306	li	r9,0
307
308	/* load up the pir */
309	lwz	r0,ENTRY_PIR(r10)
310	mtspr	SPRN_PIR,r0
311	mfspr	r0,SPRN_PIR
312	stw	r0,ENTRY_PIR(r10)
313
314	mtspr	IVPR,r12
315/*
316 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
317 * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
318 * second mapping that maps addr 1:1 for 64M, and then we jump to
319 * addr
320 */
321	lis	r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
322	mtspr	SPRN_MAS0,r10
323	lis	r10,(MAS1_VALID|MAS1_IPROT)@h
324	ori	r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
325	mtspr	SPRN_MAS1,r10
326	/* WIMGE = 0b00000 for now */
327	mtspr	SPRN_MAS2,r12
328	ori	r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
329	mtspr	SPRN_MAS3,r12
330#ifdef CONFIG_ENABLE_36BIT_PHYS
331	mtspr	SPRN_MAS7,r11
332#endif
333	tlbwe
334
335/* Now we have another mapping for this page, so we jump to that
336 * mapping
337 */
338	mtspr	SPRN_SRR1,r13
339	rfi
340
341	/*
342	 * Allocate some space for the SDRAM address of the bootpg.
343	 * This variable has to be in the boot page so that it can
344	 * be accessed by secondary cores when they come out of reset.
345	 */
346	.globl __bootpg_addr
347__bootpg_addr:
348	.long	0
349
350	.align L1_CACHE_SHIFT
351	.globl __spin_table
352__spin_table:
353	.space CONFIG_MAX_CPUS*ENTRY_SIZE
354
355	/*
356	 * This variable is set by cpu_init_r() after parsing hwconfig
357	 * to enable workaround for erratum NMG_CPU_A011.
358	 */
359	.align L1_CACHE_SHIFT
360	.global enable_cpu_a011_workaround
361enable_cpu_a011_workaround:
362	.long	1
363
364	/* Fill in the empty space.  The actual reset vector is
365	 * the last word of the page */
366__secondary_start_code_end:
367	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
368__secondary_reset_vector:
369	b	__secondary_start_page
370