1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <libfdt.h> 28 #include <fdt_support.h> 29 #include <asm/processor.h> 30 #include <linux/ctype.h> 31 #include <asm/io.h> 32 #include <asm/fsl_portals.h> 33 #ifdef CONFIG_FSL_ESDHC 34 #include <fsl_esdhc.h> 35 #endif 36 #include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */ 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 extern void ft_qe_setup(void *blob); 41 extern void ft_fixup_num_cores(void *blob); 42 extern void ft_srio_setup(void *blob); 43 44 #ifdef CONFIG_MP 45 #include "mp.h" 46 47 void ft_fixup_cpu(void *blob, u64 memory_limit) 48 { 49 int off; 50 ulong spin_tbl_addr = get_spin_phys_addr(); 51 u32 bootpg = determine_mp_bootpg(); 52 u32 id = get_my_id(); 53 const char *enable_method; 54 55 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 56 while (off != -FDT_ERR_NOTFOUND) { 57 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 58 59 if (reg) { 60 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; 61 val = cpu_to_fdt32(val); 62 if (*reg == id) { 63 fdt_setprop_string(blob, off, "status", 64 "okay"); 65 } else { 66 fdt_setprop_string(blob, off, "status", 67 "disabled"); 68 } 69 70 if (hold_cores_in_reset(0)) { 71 #ifdef CONFIG_FSL_CORENET 72 /* Cores held in reset, use BRR to release */ 73 enable_method = "fsl,brr-holdoff"; 74 #else 75 /* Cores held in reset, use EEBPCR to release */ 76 enable_method = "fsl,eebpcr-holdoff"; 77 #endif 78 } else { 79 /* Cores out of reset and in a spin-loop */ 80 enable_method = "spin-table"; 81 82 fdt_setprop(blob, off, "cpu-release-addr", 83 &val, sizeof(val)); 84 } 85 86 fdt_setprop_string(blob, off, "enable-method", 87 enable_method); 88 } else { 89 printf ("cpu NULL\n"); 90 } 91 off = fdt_node_offset_by_prop_value(blob, off, 92 "device_type", "cpu", 4); 93 } 94 95 /* Reserve the boot page so OSes dont use it */ 96 if ((u64)bootpg < memory_limit) { 97 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); 98 if (off < 0) 99 printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); 100 } 101 } 102 #endif 103 104 #ifdef CONFIG_SYS_FSL_CPC 105 static inline void ft_fixup_l3cache(void *blob, int off) 106 { 107 u32 line_size, num_ways, size, num_sets; 108 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; 109 u32 cfg0 = in_be32(&cpc->cpccfg0); 110 111 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; 112 num_ways = CPC_CFG0_NUM_WAYS(cfg0); 113 line_size = CPC_CFG0_LINE_SZ(cfg0); 114 num_sets = size / (line_size * num_ways); 115 116 fdt_setprop(blob, off, "cache-unified", NULL, 0); 117 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 118 fdt_setprop_cell(blob, off, "cache-size", size); 119 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 120 fdt_setprop_cell(blob, off, "cache-level", 3); 121 #ifdef CONFIG_SYS_CACHE_STASHING 122 fdt_setprop_cell(blob, off, "cache-stash-id", 1); 123 #endif 124 } 125 #else 126 #define ft_fixup_l3cache(x, y) 127 #endif 128 129 #if defined(CONFIG_L2_CACHE) 130 /* return size in kilobytes */ 131 static inline u32 l2cache_size(void) 132 { 133 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 134 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; 135 u32 ver = SVR_SOC_VER(get_svr()); 136 137 switch (l2siz_field) { 138 case 0x0: 139 break; 140 case 0x1: 141 if (ver == SVR_8540 || ver == SVR_8560 || 142 ver == SVR_8541 || ver == SVR_8541_E || 143 ver == SVR_8555 || ver == SVR_8555_E) 144 return 128; 145 else 146 return 256; 147 break; 148 case 0x2: 149 if (ver == SVR_8540 || ver == SVR_8560 || 150 ver == SVR_8541 || ver == SVR_8541_E || 151 ver == SVR_8555 || ver == SVR_8555_E) 152 return 256; 153 else 154 return 512; 155 break; 156 case 0x3: 157 return 1024; 158 break; 159 } 160 161 return 0; 162 } 163 164 static inline void ft_fixup_l2cache(void *blob) 165 { 166 int len, off; 167 u32 *ph; 168 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); 169 170 const u32 line_size = 32; 171 const u32 num_ways = 8; 172 const u32 size = l2cache_size() * 1024; 173 const u32 num_sets = size / (line_size * num_ways); 174 175 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 176 if (off < 0) { 177 debug("no cpu node fount\n"); 178 return; 179 } 180 181 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 182 183 if (ph == NULL) { 184 debug("no next-level-cache property\n"); 185 return ; 186 } 187 188 off = fdt_node_offset_by_phandle(blob, *ph); 189 if (off < 0) { 190 printf("%s: %s\n", __func__, fdt_strerror(off)); 191 return ; 192 } 193 194 if (cpu) { 195 char buf[40]; 196 197 if (isdigit(cpu->name[0])) { 198 /* MPCxxxx, where xxxx == 4-digit number */ 199 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", 200 cpu->name) + 1; 201 } else { 202 /* Pxxxx or Txxxx, where xxxx == 4-digit number */ 203 len = sprintf(buf, "fsl,%c%s-l2-cache-controller", 204 tolower(cpu->name[0]), cpu->name + 1) + 1; 205 } 206 207 /* 208 * append "cache" after the NULL character that the previous 209 * sprintf wrote. This is how a device tree stores multiple 210 * strings in a property. 211 */ 212 len += sprintf(buf + len, "cache") + 1; 213 214 fdt_setprop(blob, off, "compatible", buf, len); 215 } 216 fdt_setprop(blob, off, "cache-unified", NULL, 0); 217 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 218 fdt_setprop_cell(blob, off, "cache-size", size); 219 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 220 fdt_setprop_cell(blob, off, "cache-level", 2); 221 222 /* we dont bother w/L3 since no platform of this type has one */ 223 } 224 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 225 static inline void ft_fixup_l2cache(void *blob) 226 { 227 int off, l2_off, l3_off = -1; 228 u32 *ph; 229 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 230 u32 size, line_size, num_ways, num_sets; 231 232 size = (l2cfg0 & 0x3fff) * 64 * 1024; 233 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; 234 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; 235 num_sets = size / (line_size * num_ways); 236 237 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 238 239 while (off != -FDT_ERR_NOTFOUND) { 240 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 241 242 if (ph == NULL) { 243 debug("no next-level-cache property\n"); 244 goto next; 245 } 246 247 l2_off = fdt_node_offset_by_phandle(blob, *ph); 248 if (l2_off < 0) { 249 printf("%s: %s\n", __func__, fdt_strerror(off)); 250 goto next; 251 } 252 253 #ifdef CONFIG_SYS_CACHE_STASHING 254 { 255 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 256 if (reg) 257 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 258 (*reg * 2) + 32 + 1); 259 } 260 #endif 261 262 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); 263 fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); 264 fdt_setprop_cell(blob, l2_off, "cache-size", size); 265 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); 266 fdt_setprop_cell(blob, l2_off, "cache-level", 2); 267 fdt_setprop(blob, l2_off, "compatible", "cache", 6); 268 269 if (l3_off < 0) { 270 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); 271 272 if (ph == NULL) { 273 debug("no next-level-cache property\n"); 274 goto next; 275 } 276 l3_off = *ph; 277 } 278 next: 279 off = fdt_node_offset_by_prop_value(blob, off, 280 "device_type", "cpu", 4); 281 } 282 if (l3_off > 0) { 283 l3_off = fdt_node_offset_by_phandle(blob, l3_off); 284 if (l3_off < 0) { 285 printf("%s: %s\n", __func__, fdt_strerror(off)); 286 return ; 287 } 288 ft_fixup_l3cache(blob, l3_off); 289 } 290 } 291 #else 292 #define ft_fixup_l2cache(x) 293 #endif 294 295 static inline void ft_fixup_cache(void *blob) 296 { 297 int off; 298 299 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 300 301 while (off != -FDT_ERR_NOTFOUND) { 302 u32 l1cfg0 = mfspr(SPRN_L1CFG0); 303 u32 l1cfg1 = mfspr(SPRN_L1CFG1); 304 u32 isize, iline_size, inum_sets, inum_ways; 305 u32 dsize, dline_size, dnum_sets, dnum_ways; 306 307 /* d-side config */ 308 dsize = (l1cfg0 & 0x7ff) * 1024; 309 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; 310 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; 311 dnum_sets = dsize / (dline_size * dnum_ways); 312 313 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); 314 fdt_setprop_cell(blob, off, "d-cache-size", dsize); 315 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); 316 317 #ifdef CONFIG_SYS_CACHE_STASHING 318 { 319 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 320 if (reg) 321 fdt_setprop_cell(blob, off, "cache-stash-id", 322 (*reg * 2) + 32 + 0); 323 } 324 #endif 325 326 /* i-side config */ 327 isize = (l1cfg1 & 0x7ff) * 1024; 328 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; 329 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; 330 inum_sets = isize / (iline_size * inum_ways); 331 332 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); 333 fdt_setprop_cell(blob, off, "i-cache-size", isize); 334 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); 335 336 off = fdt_node_offset_by_prop_value(blob, off, 337 "device_type", "cpu", 4); 338 } 339 340 ft_fixup_l2cache(blob); 341 } 342 343 344 void fdt_add_enet_stashing(void *fdt) 345 { 346 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); 347 348 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); 349 350 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); 351 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); 352 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); 353 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); 354 } 355 356 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) 357 static void ft_fixup_clks(void *blob, const char *compat, u32 offset, 358 unsigned long freq) 359 { 360 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; 361 int off = fdt_node_offset_by_compat_reg(blob, compat, phys); 362 363 if (off >= 0) { 364 off = fdt_setprop_cell(blob, off, "clock-frequency", freq); 365 if (off > 0) 366 printf("WARNING enable to set clock-frequency " 367 "for %s: %s\n", compat, fdt_strerror(off)); 368 } 369 } 370 371 static void ft_fixup_dpaa_clks(void *blob) 372 { 373 sys_info_t sysinfo; 374 375 get_sys_info(&sysinfo); 376 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, 377 sysinfo.freqFMan[0]); 378 379 #if (CONFIG_SYS_NUM_FMAN == 2) 380 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, 381 sysinfo.freqFMan[1]); 382 #endif 383 384 #ifdef CONFIG_SYS_DPAA_PME 385 do_fixup_by_compat_u32(blob, "fsl,pme", 386 "clock-frequency", sysinfo.freqPME, 1); 387 #endif 388 } 389 #else 390 #define ft_fixup_dpaa_clks(x) 391 #endif 392 393 #ifdef CONFIG_QE 394 static void ft_fixup_qe_snum(void *blob) 395 { 396 unsigned int svr; 397 398 svr = mfspr(SPRN_SVR); 399 if (SVR_SOC_VER(svr) == SVR_8569_E) { 400 if(IS_SVR_REV(svr, 1, 0)) 401 do_fixup_by_compat_u32(blob, "fsl,qe", 402 "fsl,qe-num-snums", 46, 1); 403 else 404 do_fixup_by_compat_u32(blob, "fsl,qe", 405 "fsl,qe-num-snums", 76, 1); 406 } 407 } 408 #endif 409 410 /** 411 * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree 412 * 413 * The binding for an Fman firmware node is documented in 414 * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains 415 * the actual Fman firmware binary data. The operating system is expected to 416 * be able to parse the binary data to determine any attributes it needs. 417 */ 418 #ifdef CONFIG_SYS_DPAA_FMAN 419 void fdt_fixup_fman_firmware(void *blob) 420 { 421 int rc, fmnode, fwnode = -1; 422 uint32_t phandle; 423 struct qe_firmware *fmanfw; 424 const struct qe_header *hdr; 425 unsigned int length; 426 uint32_t crc; 427 const char *p; 428 429 /* The first Fman we find will contain the actual firmware. */ 430 fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman"); 431 if (fmnode < 0) 432 /* Exit silently if there are no Fman devices */ 433 return; 434 435 /* If we already have a firmware node, then also exit silently. */ 436 if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0) 437 return; 438 439 /* If the environment variable is not set, then exit silently */ 440 p = getenv("fman_ucode"); 441 if (!p) 442 return; 443 444 fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 0); 445 if (!fmanfw) 446 return; 447 448 hdr = &fmanfw->header; 449 length = be32_to_cpu(hdr->length); 450 451 /* Verify the firmware. */ 452 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || 453 (hdr->magic[2] != 'F')) { 454 printf("Data at %p is not an Fman firmware\n", fmanfw); 455 return; 456 } 457 458 if (length > CONFIG_SYS_FMAN_FW_LENGTH) { 459 printf("Fman firmware at %p is too large (size=%u)\n", 460 fmanfw, length); 461 return; 462 } 463 464 length -= sizeof(u32); /* Subtract the size of the CRC */ 465 crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length)); 466 if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { 467 printf("Fman firmware at %p has invalid CRC\n", fmanfw); 468 return; 469 } 470 471 /* Increase the size of the fdt to make room for the node. */ 472 rc = fdt_increase_size(blob, fmanfw->header.length); 473 if (rc < 0) { 474 printf("Unable to make room for Fman firmware: %s\n", 475 fdt_strerror(rc)); 476 return; 477 } 478 479 /* Create the firmware node. */ 480 fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware"); 481 if (fwnode < 0) { 482 char s[64]; 483 fdt_get_path(blob, fmnode, s, sizeof(s)); 484 printf("Could not add firmware node to %s: %s\n", s, 485 fdt_strerror(fwnode)); 486 return; 487 } 488 rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware"); 489 if (rc < 0) { 490 char s[64]; 491 fdt_get_path(blob, fwnode, s, sizeof(s)); 492 printf("Could not add compatible property to node %s: %s\n", s, 493 fdt_strerror(rc)); 494 return; 495 } 496 phandle = fdt_alloc_phandle(blob); 497 rc = fdt_setprop_cell(blob, fwnode, "linux,phandle", phandle); 498 if (rc < 0) { 499 char s[64]; 500 fdt_get_path(blob, fwnode, s, sizeof(s)); 501 printf("Could not add phandle property to node %s: %s\n", s, 502 fdt_strerror(rc)); 503 return; 504 } 505 rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length); 506 if (rc < 0) { 507 char s[64]; 508 fdt_get_path(blob, fwnode, s, sizeof(s)); 509 printf("Could not add firmware property to node %s: %s\n", s, 510 fdt_strerror(rc)); 511 return; 512 } 513 514 /* Find all other Fman nodes and point them to the firmware node. */ 515 while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) { 516 rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle); 517 if (rc < 0) { 518 char s[64]; 519 fdt_get_path(blob, fmnode, s, sizeof(s)); 520 printf("Could not add pointer property to node %s: %s\n", 521 s, fdt_strerror(rc)); 522 return; 523 } 524 } 525 } 526 #else 527 #define fdt_fixup_fman_firmware(x) 528 #endif 529 530 void ft_cpu_setup(void *blob, bd_t *bd) 531 { 532 int off; 533 int val; 534 sys_info_t sysinfo; 535 536 /* delete crypto node if not on an E-processor */ 537 if (!IS_E_PROCESSOR(get_svr())) 538 fdt_fixup_crypto_node(blob, 0); 539 540 fdt_fixup_ethernet(blob); 541 542 fdt_add_enet_stashing(blob); 543 544 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 545 "timebase-frequency", get_tbclk(), 1); 546 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 547 "bus-frequency", bd->bi_busfreq, 1); 548 get_sys_info(&sysinfo); 549 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 550 while (off != -FDT_ERR_NOTFOUND) { 551 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 552 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]); 553 fdt_setprop(blob, off, "clock-frequency", &val, 4); 554 off = fdt_node_offset_by_prop_value(blob, off, "device_type", 555 "cpu", 4); 556 } 557 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 558 "bus-frequency", bd->bi_busfreq, 1); 559 560 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", 561 "bus-frequency", gd->lbc_clk, 1); 562 do_fixup_by_compat_u32(blob, "fsl,elbc", 563 "bus-frequency", gd->lbc_clk, 1); 564 #ifdef CONFIG_QE 565 ft_qe_setup(blob); 566 ft_fixup_qe_snum(blob); 567 #endif 568 569 fdt_fixup_fman_firmware(blob); 570 571 #ifdef CONFIG_SYS_NS16550 572 do_fixup_by_compat_u32(blob, "ns16550", 573 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 574 #endif 575 576 #ifdef CONFIG_CPM2 577 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", 578 "current-speed", bd->bi_baudrate, 1); 579 580 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", 581 "clock-frequency", bd->bi_brgfreq, 1); 582 #endif 583 584 #ifdef CONFIG_FSL_CORENET 585 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", 586 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 587 #endif 588 589 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); 590 591 #ifdef CONFIG_MP 592 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); 593 ft_fixup_num_cores(blob); 594 #endif 595 596 ft_fixup_cache(blob); 597 598 #if defined(CONFIG_FSL_ESDHC) 599 fdt_fixup_esdhc(blob, bd); 600 #endif 601 602 ft_fixup_dpaa_clks(blob); 603 604 #if defined(CONFIG_SYS_BMAN_MEM_PHYS) 605 fdt_portal(blob, "fsl,bman-portal", "bman-portals", 606 (u64)CONFIG_SYS_BMAN_MEM_PHYS, 607 CONFIG_SYS_BMAN_MEM_SIZE); 608 fdt_fixup_bportals(blob); 609 #endif 610 611 #if defined(CONFIG_SYS_QMAN_MEM_PHYS) 612 fdt_portal(blob, "fsl,qman-portal", "qman-portals", 613 (u64)CONFIG_SYS_QMAN_MEM_PHYS, 614 CONFIG_SYS_QMAN_MEM_SIZE); 615 616 fdt_fixup_qportals(blob); 617 #endif 618 619 #ifdef CONFIG_SYS_SRIO 620 ft_srio_setup(blob); 621 #endif 622 623 /* 624 * system-clock = CCB clock/2 625 * Here gd->bus_clk = CCB clock 626 * We are using the system clock as 1588 Timer reference 627 * clock source select 628 */ 629 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", 630 "timer-frequency", gd->bus_clk/2, 1); 631 } 632