1 /* 2 * Copyright 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <asm/processor.h> 32 #include <ioports.h> 33 #include <sata.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_law.h> 37 #include <asm/fsl_serdes.h> 38 #include "mp.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 #ifdef CONFIG_MPC8536 43 extern void fsl_serdes_init(void); 44 #endif 45 46 #ifdef CONFIG_QE 47 extern qe_iop_conf_t qe_iop_conf_tab[]; 48 extern void qe_config_iopin(u8 port, u8 pin, int dir, 49 int open_drain, int assign); 50 extern void qe_init(uint qe_base); 51 extern void qe_reset(void); 52 53 static void config_qe_ioports(void) 54 { 55 u8 port, pin; 56 int dir, open_drain, assign; 57 int i; 58 59 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 60 port = qe_iop_conf_tab[i].port; 61 pin = qe_iop_conf_tab[i].pin; 62 dir = qe_iop_conf_tab[i].dir; 63 open_drain = qe_iop_conf_tab[i].open_drain; 64 assign = qe_iop_conf_tab[i].assign; 65 qe_config_iopin(port, pin, dir, open_drain, assign); 66 } 67 } 68 #endif 69 70 #ifdef CONFIG_CPM2 71 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 72 { 73 int portnum; 74 75 for (portnum = 0; portnum < 4; portnum++) { 76 uint pmsk = 0, 77 ppar = 0, 78 psor = 0, 79 pdir = 0, 80 podr = 0, 81 pdat = 0; 82 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 83 iop_conf_t *eiopc = iopc + 32; 84 uint msk = 1; 85 86 /* 87 * NOTE: 88 * index 0 refers to pin 31, 89 * index 31 refers to pin 0 90 */ 91 while (iopc < eiopc) { 92 if (iopc->conf) { 93 pmsk |= msk; 94 if (iopc->ppar) 95 ppar |= msk; 96 if (iopc->psor) 97 psor |= msk; 98 if (iopc->pdir) 99 pdir |= msk; 100 if (iopc->podr) 101 podr |= msk; 102 if (iopc->pdat) 103 pdat |= msk; 104 } 105 106 msk <<= 1; 107 iopc++; 108 } 109 110 if (pmsk != 0) { 111 volatile ioport_t *iop = ioport_addr (cpm, portnum); 112 uint tpmsk = ~pmsk; 113 114 /* 115 * the (somewhat confused) paragraph at the 116 * bottom of page 35-5 warns that there might 117 * be "unknown behaviour" when programming 118 * PSORx and PDIRx, if PPARx = 1, so I 119 * decided this meant I had to disable the 120 * dedicated function first, and enable it 121 * last. 122 */ 123 iop->ppar &= tpmsk; 124 iop->psor = (iop->psor & tpmsk) | psor; 125 iop->podr = (iop->podr & tpmsk) | podr; 126 iop->pdat = (iop->pdat & tpmsk) | pdat; 127 iop->pdir = (iop->pdir & tpmsk) | pdir; 128 iop->ppar |= ppar; 129 } 130 } 131 } 132 #endif 133 134 /* 135 * Breathe some life into the CPU... 136 * 137 * Set up the memory map 138 * initialize a bunch of registers 139 */ 140 141 #ifdef CONFIG_FSL_CORENET 142 static void corenet_tb_init(void) 143 { 144 volatile ccsr_rcpm_t *rcpm = 145 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 146 volatile ccsr_pic_t *pic = 147 (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); 148 u32 whoami = in_be32(&pic->whoami); 149 150 /* Enable the timebase register for this core */ 151 out_be32(&rcpm->ctbenrl, (1 << whoami)); 152 } 153 #endif 154 155 void cpu_init_f (void) 156 { 157 extern void m8560_cpm_reset (void); 158 #ifdef CONFIG_MPC8548 159 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 160 uint svr = get_svr(); 161 162 /* 163 * CPU2 errata workaround: A core hang possible while executing 164 * a msync instruction and a snoopable transaction from an I/O 165 * master tagged to make quick forward progress is present. 166 * Fixed in silicon rev 2.1. 167 */ 168 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 169 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 170 #endif 171 172 disable_tlb(14); 173 disable_tlb(15); 174 175 #ifdef CONFIG_CPM2 176 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 177 #endif 178 179 init_early_memctl_regs(); 180 181 #if defined(CONFIG_CPM2) 182 m8560_cpm_reset(); 183 #endif 184 #ifdef CONFIG_QE 185 /* Config QE ioports */ 186 config_qe_ioports(); 187 #endif 188 #if defined(CONFIG_MPC8536) 189 fsl_serdes_init(); 190 #endif 191 #if defined(CONFIG_FSL_DMA) 192 dma_init(); 193 #endif 194 #ifdef CONFIG_FSL_CORENET 195 corenet_tb_init(); 196 #endif 197 init_used_tlb_cams(); 198 } 199 200 201 /* 202 * Initialize L2 as cache. 203 * 204 * The newer 8548, etc, parts have twice as much cache, but 205 * use the same bit-encoding as the older 8555, etc, parts. 206 * 207 */ 208 209 int cpu_init_r(void) 210 { 211 #ifdef CONFIG_SYS_LBC_LCRR 212 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 213 #endif 214 215 puts ("L2: "); 216 217 #if defined(CONFIG_L2_CACHE) 218 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 219 volatile uint cache_ctl; 220 uint svr, ver; 221 uint l2srbar; 222 u32 l2siz_field; 223 224 svr = get_svr(); 225 ver = SVR_SOC_VER(svr); 226 227 asm("msync;isync"); 228 cache_ctl = l2cache->l2ctl; 229 230 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 231 if (cache_ctl & MPC85xx_L2CTL_L2E) { 232 /* Clear L2 SRAM memory-mapped base address */ 233 out_be32(&l2cache->l2srbar0, 0x0); 234 out_be32(&l2cache->l2srbar1, 0x0); 235 236 /* set MBECCDIS=0, SBECCDIS=0 */ 237 clrbits_be32(&l2cache->l2errdis, 238 (MPC85xx_L2ERRDIS_MBECC | 239 MPC85xx_L2ERRDIS_SBECC)); 240 241 /* set L2E=0, L2SRAM=0 */ 242 clrbits_be32(&l2cache->l2ctl, 243 (MPC85xx_L2CTL_L2E | 244 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 245 } 246 #endif 247 248 l2siz_field = (cache_ctl >> 28) & 0x3; 249 250 switch (l2siz_field) { 251 case 0x0: 252 printf(" unknown size (0x%08x)\n", cache_ctl); 253 return -1; 254 break; 255 case 0x1: 256 if (ver == SVR_8540 || ver == SVR_8560 || 257 ver == SVR_8541 || ver == SVR_8541_E || 258 ver == SVR_8555 || ver == SVR_8555_E) { 259 puts("128 KB "); 260 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 261 cache_ctl = 0xc4000000; 262 } else { 263 puts("256 KB "); 264 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 265 } 266 break; 267 case 0x2: 268 if (ver == SVR_8540 || ver == SVR_8560 || 269 ver == SVR_8541 || ver == SVR_8541_E || 270 ver == SVR_8555 || ver == SVR_8555_E) { 271 puts("256 KB "); 272 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 273 cache_ctl = 0xc8000000; 274 } else { 275 puts ("512 KB "); 276 /* set L2E=1, L2I=1, & L2SRAM=0 */ 277 cache_ctl = 0xc0000000; 278 } 279 break; 280 case 0x3: 281 puts("1024 KB "); 282 /* set L2E=1, L2I=1, & L2SRAM=0 */ 283 cache_ctl = 0xc0000000; 284 break; 285 } 286 287 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 288 puts("already enabled"); 289 l2srbar = l2cache->l2srbar0; 290 #ifdef CONFIG_SYS_INIT_L2_ADDR 291 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 292 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 293 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 294 l2cache->l2srbar0 = l2srbar; 295 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 296 } 297 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 298 puts("\n"); 299 } else { 300 asm("msync;isync"); 301 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 302 asm("msync;isync"); 303 puts("enabled\n"); 304 } 305 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 306 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 307 308 /* invalidate the L2 cache */ 309 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 310 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 311 ; 312 313 #ifdef CONFIG_SYS_CACHE_STASHING 314 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 315 mtspr(SPRN_L2CSR1, (32 + 1)); 316 #endif 317 318 /* enable the cache */ 319 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 320 321 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 322 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 323 ; 324 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 325 } 326 #else 327 puts("disabled\n"); 328 #endif 329 #ifdef CONFIG_QE 330 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 331 qe_init(qe_base); 332 qe_reset(); 333 #endif 334 335 #if defined(CONFIG_MP) 336 setup_mp(); 337 #endif 338 339 #ifdef CONFIG_SYS_LBC_LCRR 340 /* 341 * Modify the CLKDIV field of LCRR register to improve the writing 342 * speed for NOR flash. 343 */ 344 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 345 __raw_readl(&lbc->lcrr); 346 isync(); 347 #endif 348 349 return 0; 350 } 351 352 extern void setup_ivors(void); 353 354 void arch_preboot_os(void) 355 { 356 u32 msr; 357 358 /* 359 * We are changing interrupt offsets and are about to boot the OS so 360 * we need to make sure we disable all async interrupts. EE is already 361 * disabled by the time we get called. 362 */ 363 msr = mfmsr(); 364 msr &= ~(MSR_ME|MSR_CE|MSR_DE); 365 mtmsr(msr); 366 367 setup_ivors(); 368 } 369 370 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 371 int sata_initialize(void) 372 { 373 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 374 return __sata_initialize(); 375 376 return 1; 377 } 378 #endif 379