1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <asm/processor.h> 32 #include <ioports.h> 33 #include <sata.h> 34 #include <fm_eth.h> 35 #include <asm/io.h> 36 #include <asm/cache.h> 37 #include <asm/mmu.h> 38 #include <asm/fsl_law.h> 39 #include <asm/fsl_serdes.h> 40 #include <asm/fsl_srio.h> 41 #include <hwconfig.h> 42 #include <linux/compiler.h> 43 #include "mp.h" 44 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 45 #include <nand.h> 46 #include <errno.h> 47 #endif 48 49 #include "../../../../drivers/block/fsl_sata.h" 50 51 #define HWCONFIG_BUFFER_SIZE 128 52 53 DECLARE_GLOBAL_DATA_PTR; 54 55 #ifdef CONFIG_QE 56 extern qe_iop_conf_t qe_iop_conf_tab[]; 57 extern void qe_config_iopin(u8 port, u8 pin, int dir, 58 int open_drain, int assign); 59 extern void qe_init(uint qe_base); 60 extern void qe_reset(void); 61 62 static void config_qe_ioports(void) 63 { 64 u8 port, pin; 65 int dir, open_drain, assign; 66 int i; 67 68 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 69 port = qe_iop_conf_tab[i].port; 70 pin = qe_iop_conf_tab[i].pin; 71 dir = qe_iop_conf_tab[i].dir; 72 open_drain = qe_iop_conf_tab[i].open_drain; 73 assign = qe_iop_conf_tab[i].assign; 74 qe_config_iopin(port, pin, dir, open_drain, assign); 75 } 76 } 77 #endif 78 79 #ifdef CONFIG_CPM2 80 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 81 { 82 int portnum; 83 84 for (portnum = 0; portnum < 4; portnum++) { 85 uint pmsk = 0, 86 ppar = 0, 87 psor = 0, 88 pdir = 0, 89 podr = 0, 90 pdat = 0; 91 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 92 iop_conf_t *eiopc = iopc + 32; 93 uint msk = 1; 94 95 /* 96 * NOTE: 97 * index 0 refers to pin 31, 98 * index 31 refers to pin 0 99 */ 100 while (iopc < eiopc) { 101 if (iopc->conf) { 102 pmsk |= msk; 103 if (iopc->ppar) 104 ppar |= msk; 105 if (iopc->psor) 106 psor |= msk; 107 if (iopc->pdir) 108 pdir |= msk; 109 if (iopc->podr) 110 podr |= msk; 111 if (iopc->pdat) 112 pdat |= msk; 113 } 114 115 msk <<= 1; 116 iopc++; 117 } 118 119 if (pmsk != 0) { 120 volatile ioport_t *iop = ioport_addr (cpm, portnum); 121 uint tpmsk = ~pmsk; 122 123 /* 124 * the (somewhat confused) paragraph at the 125 * bottom of page 35-5 warns that there might 126 * be "unknown behaviour" when programming 127 * PSORx and PDIRx, if PPARx = 1, so I 128 * decided this meant I had to disable the 129 * dedicated function first, and enable it 130 * last. 131 */ 132 iop->ppar &= tpmsk; 133 iop->psor = (iop->psor & tpmsk) | psor; 134 iop->podr = (iop->podr & tpmsk) | podr; 135 iop->pdat = (iop->pdat & tpmsk) | pdat; 136 iop->pdir = (iop->pdir & tpmsk) | pdir; 137 iop->ppar |= ppar; 138 } 139 } 140 } 141 #endif 142 143 #ifdef CONFIG_SYS_FSL_CPC 144 static void enable_cpc(void) 145 { 146 int i; 147 u32 size = 0; 148 149 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 150 151 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 152 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 153 size += CPC_CFG0_SZ_K(cpccfg0); 154 #ifdef CONFIG_RAMBOOT_PBL 155 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 156 /* find and disable LAW of SRAM */ 157 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 158 159 if (law.index == -1) { 160 printf("\nFatal error happened\n"); 161 return; 162 } 163 disable_law(law.index); 164 165 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 166 out_be32(&cpc->cpccsr0, 0); 167 out_be32(&cpc->cpcsrcr0, 0); 168 } 169 #endif 170 171 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 172 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 173 #endif 174 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 175 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 176 #endif 177 178 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 179 /* Read back to sync write */ 180 in_be32(&cpc->cpccsr0); 181 182 } 183 184 printf("Corenet Platform Cache: %d KB enabled\n", size); 185 } 186 187 void invalidate_cpc(void) 188 { 189 int i; 190 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 191 192 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 193 /* skip CPC when it used as all SRAM */ 194 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 195 continue; 196 /* Flash invalidate the CPC and clear all the locks */ 197 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 198 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 199 ; 200 } 201 } 202 #else 203 #define enable_cpc() 204 #define invalidate_cpc() 205 #endif /* CONFIG_SYS_FSL_CPC */ 206 207 /* 208 * Breathe some life into the CPU... 209 * 210 * Set up the memory map 211 * initialize a bunch of registers 212 */ 213 214 #ifdef CONFIG_FSL_CORENET 215 static void corenet_tb_init(void) 216 { 217 volatile ccsr_rcpm_t *rcpm = 218 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 219 volatile ccsr_pic_t *pic = 220 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 221 u32 whoami = in_be32(&pic->whoami); 222 223 /* Enable the timebase register for this core */ 224 out_be32(&rcpm->ctbenrl, (1 << whoami)); 225 } 226 #endif 227 228 void cpu_init_f (void) 229 { 230 extern void m8560_cpm_reset (void); 231 #ifdef CONFIG_SYS_DCSRBAR_PHYS 232 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 233 #endif 234 #if defined(CONFIG_SECURE_BOOT) 235 struct law_entry law; 236 #endif 237 #ifdef CONFIG_MPC8548 238 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 239 uint svr = get_svr(); 240 241 /* 242 * CPU2 errata workaround: A core hang possible while executing 243 * a msync instruction and a snoopable transaction from an I/O 244 * master tagged to make quick forward progress is present. 245 * Fixed in silicon rev 2.1. 246 */ 247 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 248 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 249 #endif 250 251 disable_tlb(14); 252 disable_tlb(15); 253 254 #if defined(CONFIG_SECURE_BOOT) 255 /* Disable the LAW created for NOR flash by the PBI commands */ 256 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 257 if (law.index != -1) 258 disable_law(law.index); 259 #endif 260 261 #ifdef CONFIG_CPM2 262 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 263 #endif 264 265 init_early_memctl_regs(); 266 267 #if defined(CONFIG_CPM2) 268 m8560_cpm_reset(); 269 #endif 270 #ifdef CONFIG_QE 271 /* Config QE ioports */ 272 config_qe_ioports(); 273 #endif 274 #if defined(CONFIG_FSL_DMA) 275 dma_init(); 276 #endif 277 #ifdef CONFIG_FSL_CORENET 278 corenet_tb_init(); 279 #endif 280 init_used_tlb_cams(); 281 282 /* Invalidate the CPC before DDR gets enabled */ 283 invalidate_cpc(); 284 285 #ifdef CONFIG_SYS_DCSRBAR_PHYS 286 /* set DCSRCR so that DCSR space is 1G */ 287 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 288 in_be32(&gur->dcsrcr); 289 #endif 290 291 } 292 293 /* Implement a dummy function for those platforms w/o SERDES */ 294 static void __fsl_serdes__init(void) 295 { 296 return ; 297 } 298 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 299 300 /* 301 * Initialize L2 as cache. 302 * 303 * The newer 8548, etc, parts have twice as much cache, but 304 * use the same bit-encoding as the older 8555, etc, parts. 305 * 306 */ 307 int cpu_init_r(void) 308 { 309 __maybe_unused u32 svr = get_svr(); 310 #ifdef CONFIG_SYS_LBC_LCRR 311 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 312 #endif 313 314 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 315 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 316 /* 317 * CPU22 and NMG_CPU_A011 share the same workaround. 318 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 319 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 320 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 321 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 322 * be disabled by hwconfig with syntax: 323 * 324 * fsl_cpu_a011:disable 325 */ 326 extern int enable_cpu_a011_workaround; 327 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 328 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 329 #else 330 char buffer[HWCONFIG_BUFFER_SIZE]; 331 char *buf = NULL; 332 int n, res; 333 334 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 335 if (n > 0) 336 buf = buffer; 337 338 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 339 if (res > 0) 340 enable_cpu_a011_workaround = 0; 341 else { 342 if (n >= HWCONFIG_BUFFER_SIZE) { 343 printf("fsl_cpu_a011 was not found. hwconfig variable " 344 "may be too long\n"); 345 } 346 enable_cpu_a011_workaround = 347 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 348 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 349 } 350 #endif 351 if (enable_cpu_a011_workaround) { 352 flush_dcache(); 353 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 354 sync(); 355 } 356 #endif 357 358 puts ("L2: "); 359 360 #if defined(CONFIG_L2_CACHE) 361 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 362 volatile uint cache_ctl; 363 uint ver; 364 u32 l2siz_field; 365 366 ver = SVR_SOC_VER(svr); 367 368 asm("msync;isync"); 369 cache_ctl = l2cache->l2ctl; 370 371 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 372 if (cache_ctl & MPC85xx_L2CTL_L2E) { 373 /* Clear L2 SRAM memory-mapped base address */ 374 out_be32(&l2cache->l2srbar0, 0x0); 375 out_be32(&l2cache->l2srbar1, 0x0); 376 377 /* set MBECCDIS=0, SBECCDIS=0 */ 378 clrbits_be32(&l2cache->l2errdis, 379 (MPC85xx_L2ERRDIS_MBECC | 380 MPC85xx_L2ERRDIS_SBECC)); 381 382 /* set L2E=0, L2SRAM=0 */ 383 clrbits_be32(&l2cache->l2ctl, 384 (MPC85xx_L2CTL_L2E | 385 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 386 } 387 #endif 388 389 l2siz_field = (cache_ctl >> 28) & 0x3; 390 391 switch (l2siz_field) { 392 case 0x0: 393 printf(" unknown size (0x%08x)\n", cache_ctl); 394 return -1; 395 break; 396 case 0x1: 397 if (ver == SVR_8540 || ver == SVR_8560 || 398 ver == SVR_8541 || ver == SVR_8555) { 399 puts("128 KB "); 400 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 401 cache_ctl = 0xc4000000; 402 } else { 403 puts("256 KB "); 404 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 405 } 406 break; 407 case 0x2: 408 if (ver == SVR_8540 || ver == SVR_8560 || 409 ver == SVR_8541 || ver == SVR_8555) { 410 puts("256 KB "); 411 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 412 cache_ctl = 0xc8000000; 413 } else { 414 puts ("512 KB "); 415 /* set L2E=1, L2I=1, & L2SRAM=0 */ 416 cache_ctl = 0xc0000000; 417 } 418 break; 419 case 0x3: 420 puts("1024 KB "); 421 /* set L2E=1, L2I=1, & L2SRAM=0 */ 422 cache_ctl = 0xc0000000; 423 break; 424 } 425 426 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 427 puts("already enabled"); 428 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 429 u32 l2srbar = l2cache->l2srbar0; 430 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 431 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 432 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 433 l2cache->l2srbar0 = l2srbar; 434 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 435 } 436 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 437 puts("\n"); 438 } else { 439 asm("msync;isync"); 440 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 441 asm("msync;isync"); 442 puts("enabled\n"); 443 } 444 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 445 if (SVR_SOC_VER(svr) == SVR_P2040) { 446 puts("N/A\n"); 447 goto skip_l2; 448 } 449 450 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 451 452 /* invalidate the L2 cache */ 453 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 454 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 455 ; 456 457 #ifdef CONFIG_SYS_CACHE_STASHING 458 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 459 mtspr(SPRN_L2CSR1, (32 + 1)); 460 #endif 461 462 /* enable the cache */ 463 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 464 465 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 466 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 467 ; 468 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 469 } 470 471 skip_l2: 472 #else 473 puts("disabled\n"); 474 #endif 475 476 enable_cpc(); 477 478 /* needs to be in ram since code uses global static vars */ 479 fsl_serdes_init(); 480 481 #ifdef CONFIG_SYS_SRIO 482 srio_init(); 483 #ifdef CONFIG_FSL_CORENET 484 char *s = getenv("bootmaster"); 485 if (s) { 486 if (!strcmp(s, "SRIO1")) { 487 srio_boot_master(1); 488 srio_boot_master_release_slave(1); 489 } 490 if (!strcmp(s, "SRIO2")) { 491 srio_boot_master(2); 492 srio_boot_master_release_slave(2); 493 } 494 } 495 #endif 496 #endif 497 498 #if defined(CONFIG_MP) 499 setup_mp(); 500 #endif 501 502 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136 503 { 504 void *p; 505 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 506 setbits_be32(p, 1 << (31 - 14)); 507 } 508 #endif 509 510 #ifdef CONFIG_SYS_LBC_LCRR 511 /* 512 * Modify the CLKDIV field of LCRR register to improve the writing 513 * speed for NOR flash. 514 */ 515 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 516 __raw_readl(&lbc->lcrr); 517 isync(); 518 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 519 udelay(100); 520 #endif 521 #endif 522 523 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 524 { 525 ccsr_usb_phy_t *usb_phy1 = 526 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 527 out_be32(&usb_phy1->usb_enable_override, 528 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 529 } 530 #endif 531 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 532 { 533 ccsr_usb_phy_t *usb_phy2 = 534 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 535 out_be32(&usb_phy2->usb_enable_override, 536 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 537 } 538 #endif 539 540 #ifdef CONFIG_FMAN_ENET 541 fman_enet_init(); 542 #endif 543 544 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 545 /* 546 * For P1022/1013 Rev1.0 silicon, after power on SATA host 547 * controller is configured in legacy mode instead of the 548 * expected enterprise mode. Software needs to clear bit[28] 549 * of HControl register to change to enterprise mode from 550 * legacy mode. We assume that the controller is offline. 551 */ 552 if (IS_SVR_REV(svr, 1, 0) && 553 ((SVR_SOC_VER(svr) == SVR_P1022) || 554 (SVR_SOC_VER(svr) == SVR_P1013))) { 555 fsl_sata_reg_t *reg; 556 557 /* first SATA controller */ 558 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 559 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 560 561 /* second SATA controller */ 562 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 563 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 564 } 565 #endif 566 567 568 return 0; 569 } 570 571 extern void setup_ivors(void); 572 573 void arch_preboot_os(void) 574 { 575 u32 msr; 576 577 /* 578 * We are changing interrupt offsets and are about to boot the OS so 579 * we need to make sure we disable all async interrupts. EE is already 580 * disabled by the time we get called. 581 */ 582 msr = mfmsr(); 583 msr &= ~(MSR_ME|MSR_CE); 584 mtmsr(msr); 585 586 setup_ivors(); 587 } 588 589 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 590 int sata_initialize(void) 591 { 592 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 593 return __sata_initialize(); 594 595 return 1; 596 } 597 #endif 598 599 void cpu_secondary_init_r(void) 600 { 601 #ifdef CONFIG_QE 602 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 603 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 604 int ret; 605 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; 606 607 /* load QE firmware from NAND flash to DDR first */ 608 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, 609 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); 610 611 if (ret && ret == -EUCLEAN) { 612 printf ("NAND read for QE firmware at offset %x failed %d\n", 613 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); 614 } 615 #endif 616 qe_init(qe_base); 617 qe_reset(); 618 #endif 619 } 620