1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <asm/fsl_errata.h> 23 #include <asm/fsl_law.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/fsl_srio.h> 26 #include <fsl_usb.h> 27 #include <hwconfig.h> 28 #include <linux/compiler.h> 29 #include "mp.h" 30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 31 #include <nand.h> 32 #include <errno.h> 33 #endif 34 35 #include "../../../../drivers/block/fsl_sata.h" 36 #ifdef CONFIG_U_QE 37 #include "../../../../drivers/qe/qe.h" 38 #endif 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 43 /* 44 * For deriving usb clock from 100MHz sysclk, reference divisor is set 45 * to a value of 5, which gives an intermediate value 20(100/5). The 46 * multiplication factor integer is set to 24, which when multiplied to 47 * above intermediate value provides clock for usb ip. 48 */ 49 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) 50 { 51 sys_info_t sysinfo; 52 53 get_sys_info(&sysinfo); 54 if (sysinfo.diff_sysclk == 1) { 55 clrbits_be32(&usb_phy->pllprg[1], 56 CONFIG_SYS_FSL_USB_PLLPRG2_MFI); 57 setbits_be32(&usb_phy->pllprg[1], 58 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | 59 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | 60 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); 61 } 62 } 63 #endif 64 65 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 66 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) 67 { 68 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 69 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); 70 71 /* Increase Disconnect Threshold by 50mV */ 72 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 73 INC_DCNT_THRESHOLD_50MV; 74 /* Enable programming of USB High speed Disconnect threshold */ 75 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 76 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); 77 78 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); 79 /* Increase Disconnect Threshold by 50mV */ 80 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 81 INC_DCNT_THRESHOLD_50MV; 82 /* Enable programming of USB High speed Disconnect threshold */ 83 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 84 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); 85 #else 86 87 u32 temp = 0; 88 u32 status = in_be32(&usb_phy->status1); 89 90 u32 squelch_prog_rd_0_2 = 91 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) 92 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 93 94 u32 squelch_prog_rd_3_5 = 95 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) 96 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 97 98 setbits_be32(&usb_phy->config1, 99 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); 100 setbits_be32(&usb_phy->config2, 101 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); 102 103 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; 104 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 105 106 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; 107 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 108 #endif 109 } 110 #endif 111 112 113 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 114 extern qe_iop_conf_t qe_iop_conf_tab[]; 115 extern void qe_config_iopin(u8 port, u8 pin, int dir, 116 int open_drain, int assign); 117 extern void qe_init(uint qe_base); 118 extern void qe_reset(void); 119 120 static void config_qe_ioports(void) 121 { 122 u8 port, pin; 123 int dir, open_drain, assign; 124 int i; 125 126 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 127 port = qe_iop_conf_tab[i].port; 128 pin = qe_iop_conf_tab[i].pin; 129 dir = qe_iop_conf_tab[i].dir; 130 open_drain = qe_iop_conf_tab[i].open_drain; 131 assign = qe_iop_conf_tab[i].assign; 132 qe_config_iopin(port, pin, dir, open_drain, assign); 133 } 134 } 135 #endif 136 137 #ifdef CONFIG_CPM2 138 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 139 { 140 int portnum; 141 142 for (portnum = 0; portnum < 4; portnum++) { 143 uint pmsk = 0, 144 ppar = 0, 145 psor = 0, 146 pdir = 0, 147 podr = 0, 148 pdat = 0; 149 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 150 iop_conf_t *eiopc = iopc + 32; 151 uint msk = 1; 152 153 /* 154 * NOTE: 155 * index 0 refers to pin 31, 156 * index 31 refers to pin 0 157 */ 158 while (iopc < eiopc) { 159 if (iopc->conf) { 160 pmsk |= msk; 161 if (iopc->ppar) 162 ppar |= msk; 163 if (iopc->psor) 164 psor |= msk; 165 if (iopc->pdir) 166 pdir |= msk; 167 if (iopc->podr) 168 podr |= msk; 169 if (iopc->pdat) 170 pdat |= msk; 171 } 172 173 msk <<= 1; 174 iopc++; 175 } 176 177 if (pmsk != 0) { 178 volatile ioport_t *iop = ioport_addr (cpm, portnum); 179 uint tpmsk = ~pmsk; 180 181 /* 182 * the (somewhat confused) paragraph at the 183 * bottom of page 35-5 warns that there might 184 * be "unknown behaviour" when programming 185 * PSORx and PDIRx, if PPARx = 1, so I 186 * decided this meant I had to disable the 187 * dedicated function first, and enable it 188 * last. 189 */ 190 iop->ppar &= tpmsk; 191 iop->psor = (iop->psor & tpmsk) | psor; 192 iop->podr = (iop->podr & tpmsk) | podr; 193 iop->pdat = (iop->pdat & tpmsk) | pdat; 194 iop->pdir = (iop->pdir & tpmsk) | pdir; 195 iop->ppar |= ppar; 196 } 197 } 198 } 199 #endif 200 201 #ifdef CONFIG_SYS_FSL_CPC 202 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) 203 static void disable_cpc_sram(void) 204 { 205 int i; 206 207 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 208 209 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 210 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 211 /* find and disable LAW of SRAM */ 212 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 213 214 if (law.index == -1) { 215 printf("\nFatal error happened\n"); 216 return; 217 } 218 disable_law(law.index); 219 220 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 221 out_be32(&cpc->cpccsr0, 0); 222 out_be32(&cpc->cpcsrcr0, 0); 223 } 224 } 225 } 226 #endif 227 228 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 229 #ifdef CONFIG_POST 230 #error POST memory test cannot be enabled with TDM 231 #endif 232 static void enable_tdm_law(void) 233 { 234 int ret; 235 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 236 int tdm_hwconfig_enabled = 0; 237 238 /* 239 * Extract hwconfig from environment since environment 240 * is not setup properly yet. Search for tdm entry in 241 * hwconfig. 242 */ 243 ret = getenv_f("hwconfig", buffer, sizeof(buffer)); 244 if (ret > 0) { 245 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); 246 /* If tdm is defined in hwconfig, set law for tdm workaround */ 247 if (tdm_hwconfig_enabled) 248 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M, 249 LAW_TRGT_IF_CCSR); 250 } 251 } 252 #endif 253 254 static void enable_cpc(void) 255 { 256 int i; 257 u32 size = 0; 258 259 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 260 261 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 262 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 263 size += CPC_CFG0_SZ_K(cpccfg0); 264 265 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 266 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 267 #endif 268 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 269 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 270 #endif 271 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 272 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 273 #endif 274 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 275 if (has_erratum_a006379()) { 276 setbits_be32(&cpc->cpchdbcr0, 277 CPC_HDBCR0_SPLRU_LEVEL_EN); 278 } 279 #endif 280 281 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 282 /* Read back to sync write */ 283 in_be32(&cpc->cpccsr0); 284 285 } 286 287 puts("Corenet Platform Cache: "); 288 print_size(size * 1024, " enabled\n"); 289 } 290 291 static void invalidate_cpc(void) 292 { 293 int i; 294 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 295 296 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 297 /* skip CPC when it used as all SRAM */ 298 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 299 continue; 300 /* Flash invalidate the CPC and clear all the locks */ 301 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 302 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 303 ; 304 } 305 } 306 #else 307 #define enable_cpc() 308 #define invalidate_cpc() 309 #endif /* CONFIG_SYS_FSL_CPC */ 310 311 /* 312 * Breathe some life into the CPU... 313 * 314 * Set up the memory map 315 * initialize a bunch of registers 316 */ 317 318 #ifdef CONFIG_FSL_CORENET 319 static void corenet_tb_init(void) 320 { 321 volatile ccsr_rcpm_t *rcpm = 322 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 323 volatile ccsr_pic_t *pic = 324 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 325 u32 whoami = in_be32(&pic->whoami); 326 327 /* Enable the timebase register for this core */ 328 out_be32(&rcpm->ctbenrl, (1 << whoami)); 329 } 330 #endif 331 332 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 333 void fsl_erratum_a007212_workaround(void) 334 { 335 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 336 u32 ddr_pll_ratio; 337 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); 338 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); 339 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); 340 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 341 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); 342 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); 343 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 344 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); 345 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); 346 #endif 347 #endif 348 /* 349 * Even this workaround applies to selected version of SoCs, it is 350 * safe to apply to all versions, with the limitation of odd ratios. 351 * If RCW has disabled DDR PLL, we have to apply this workaround, 352 * otherwise DDR will not work. 353 */ 354 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 355 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & 356 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 357 /* check if RCW sets ratio to 0, required by this workaround */ 358 if (ddr_pll_ratio != 0) 359 return; 360 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 361 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 362 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 363 /* check if reserved bits have the desired ratio */ 364 if (ddr_pll_ratio == 0) { 365 printf("Error: Unknown DDR PLL ratio!\n"); 366 return; 367 } 368 ddr_pll_ratio >>= 1; 369 370 setbits_be32(plldadcr1, 0x02000001); 371 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 372 setbits_be32(plldadcr2, 0x02000001); 373 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 374 setbits_be32(plldadcr3, 0x02000001); 375 #endif 376 #endif 377 setbits_be32(dpdovrcr4, 0xe0000000); 378 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); 379 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 380 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); 381 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 382 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); 383 #endif 384 #endif 385 udelay(100); 386 clrbits_be32(plldadcr1, 0x02000001); 387 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 388 clrbits_be32(plldadcr2, 0x02000001); 389 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 390 clrbits_be32(plldadcr3, 0x02000001); 391 #endif 392 #endif 393 clrbits_be32(dpdovrcr4, 0xe0000000); 394 } 395 #endif 396 397 ulong cpu_init_f(void) 398 { 399 ulong flag = 0; 400 extern void m8560_cpm_reset (void); 401 #ifdef CONFIG_SYS_DCSRBAR_PHYS 402 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 403 #endif 404 #if defined(CONFIG_SECURE_BOOT) 405 struct law_entry law; 406 #endif 407 #ifdef CONFIG_MPC8548 408 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 409 uint svr = get_svr(); 410 411 /* 412 * CPU2 errata workaround: A core hang possible while executing 413 * a msync instruction and a snoopable transaction from an I/O 414 * master tagged to make quick forward progress is present. 415 * Fixed in silicon rev 2.1. 416 */ 417 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 418 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 419 #endif 420 421 disable_tlb(14); 422 disable_tlb(15); 423 424 #if defined(CONFIG_SECURE_BOOT) 425 /* Disable the LAW created for NOR flash by the PBI commands */ 426 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 427 if (law.index != -1) 428 disable_law(law.index); 429 430 #if defined(CONFIG_SYS_CPC_REINIT_F) 431 disable_cpc_sram(); 432 #endif 433 #endif 434 435 #ifdef CONFIG_CPM2 436 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 437 #endif 438 439 init_early_memctl_regs(); 440 441 #if defined(CONFIG_CPM2) 442 m8560_cpm_reset(); 443 #endif 444 445 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 446 /* Config QE ioports */ 447 config_qe_ioports(); 448 #endif 449 450 #if defined(CONFIG_FSL_DMA) 451 dma_init(); 452 #endif 453 #ifdef CONFIG_FSL_CORENET 454 corenet_tb_init(); 455 #endif 456 init_used_tlb_cams(); 457 458 /* Invalidate the CPC before DDR gets enabled */ 459 invalidate_cpc(); 460 461 #ifdef CONFIG_SYS_DCSRBAR_PHYS 462 /* set DCSRCR so that DCSR space is 1G */ 463 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 464 in_be32(&gur->dcsrcr); 465 #endif 466 467 #ifdef CONFIG_SYS_DCSRBAR_PHYS 468 #ifdef CONFIG_DEEP_SLEEP 469 /* disable the console if boot from deep sleep */ 470 if (in_be32(&gur->scrtsr[0]) & (1 << 3)) 471 flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; 472 #endif 473 #endif 474 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 475 fsl_erratum_a007212_workaround(); 476 #endif 477 478 return flag; 479 } 480 481 /* Implement a dummy function for those platforms w/o SERDES */ 482 static void __fsl_serdes__init(void) 483 { 484 return ; 485 } 486 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 487 488 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 489 int enable_cluster_l2(void) 490 { 491 int i = 0; 492 u32 cluster, svr = get_svr(); 493 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 494 struct ccsr_cluster_l2 __iomem *l2cache; 495 496 /* only the L2 of first cluster should be enabled as expected on T4080, 497 * but there is no EOC in the first cluster as HW sake, so return here 498 * to skip enabling L2 cache of the 2nd cluster. 499 */ 500 if (SVR_SOC_VER(svr) == SVR_T4080) 501 return 0; 502 503 cluster = in_be32(&gur->tp_cluster[i].lower); 504 if (cluster & TP_CLUSTER_EOC) 505 return 0; 506 507 /* The first cache has already been set up, so skip it */ 508 i++; 509 510 /* Look through the remaining clusters, and set up their caches */ 511 do { 512 int j, cluster_valid = 0; 513 514 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 515 516 cluster = in_be32(&gur->tp_cluster[i].lower); 517 518 /* check that at least one core/accel is enabled in cluster */ 519 for (j = 0; j < 4; j++) { 520 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 521 u32 type = in_be32(&gur->tp_ityp[idx]); 522 523 if (type & TP_ITYP_AV) 524 cluster_valid = 1; 525 } 526 527 if (cluster_valid) { 528 /* set stash ID to (cluster) * 2 + 32 + 1 */ 529 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 530 531 printf("enable l2 for cluster %d %p\n", i, l2cache); 532 533 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 534 while ((in_be32(&l2cache->l2csr0) 535 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 536 ; 537 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 538 } 539 i++; 540 } while (!(cluster & TP_CLUSTER_EOC)); 541 542 return 0; 543 } 544 #endif 545 546 /* 547 * Initialize L2 as cache. 548 * 549 * The newer 8548, etc, parts have twice as much cache, but 550 * use the same bit-encoding as the older 8555, etc, parts. 551 * 552 */ 553 int cpu_init_r(void) 554 { 555 __maybe_unused u32 svr = get_svr(); 556 #ifdef CONFIG_SYS_LBC_LCRR 557 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 558 #endif 559 #ifdef CONFIG_L2_CACHE 560 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 561 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 562 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 563 #endif 564 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 565 extern int spin_table_compat; 566 const char *spin; 567 #endif 568 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 569 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 570 #endif 571 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 572 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 573 /* 574 * CPU22 and NMG_CPU_A011 share the same workaround. 575 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 576 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 577 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 578 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 579 * be disabled by hwconfig with syntax: 580 * 581 * fsl_cpu_a011:disable 582 */ 583 extern int enable_cpu_a011_workaround; 584 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 585 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 586 #else 587 char buffer[HWCONFIG_BUFFER_SIZE]; 588 char *buf = NULL; 589 int n, res; 590 591 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 592 if (n > 0) 593 buf = buffer; 594 595 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 596 if (res > 0) 597 enable_cpu_a011_workaround = 0; 598 else { 599 if (n >= HWCONFIG_BUFFER_SIZE) { 600 printf("fsl_cpu_a011 was not found. hwconfig variable " 601 "may be too long\n"); 602 } 603 enable_cpu_a011_workaround = 604 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 605 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 606 } 607 #endif 608 if (enable_cpu_a011_workaround) { 609 flush_dcache(); 610 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 611 sync(); 612 } 613 #endif 614 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 615 /* 616 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 617 * in write shadow mode. Checking DCWS before setting SPR 976. 618 */ 619 if (mfspr(L1CSR2) & L1CSR2_DCWS) 620 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 621 #endif 622 623 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 624 spin = getenv("spin_table_compat"); 625 if (spin && (*spin == 'n')) 626 spin_table_compat = 0; 627 else 628 spin_table_compat = 1; 629 #endif 630 631 puts ("L2: "); 632 633 #if defined(CONFIG_L2_CACHE) 634 volatile uint cache_ctl; 635 uint ver; 636 u32 l2siz_field; 637 638 ver = SVR_SOC_VER(svr); 639 640 asm("msync;isync"); 641 cache_ctl = l2cache->l2ctl; 642 643 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 644 if (cache_ctl & MPC85xx_L2CTL_L2E) { 645 /* Clear L2 SRAM memory-mapped base address */ 646 out_be32(&l2cache->l2srbar0, 0x0); 647 out_be32(&l2cache->l2srbar1, 0x0); 648 649 /* set MBECCDIS=0, SBECCDIS=0 */ 650 clrbits_be32(&l2cache->l2errdis, 651 (MPC85xx_L2ERRDIS_MBECC | 652 MPC85xx_L2ERRDIS_SBECC)); 653 654 /* set L2E=0, L2SRAM=0 */ 655 clrbits_be32(&l2cache->l2ctl, 656 (MPC85xx_L2CTL_L2E | 657 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 658 } 659 #endif 660 661 l2siz_field = (cache_ctl >> 28) & 0x3; 662 663 switch (l2siz_field) { 664 case 0x0: 665 printf(" unknown size (0x%08x)\n", cache_ctl); 666 return -1; 667 break; 668 case 0x1: 669 if (ver == SVR_8540 || ver == SVR_8560 || 670 ver == SVR_8541 || ver == SVR_8555) { 671 puts("128 KiB "); 672 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 673 cache_ctl = 0xc4000000; 674 } else { 675 puts("256 KiB "); 676 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 677 } 678 break; 679 case 0x2: 680 if (ver == SVR_8540 || ver == SVR_8560 || 681 ver == SVR_8541 || ver == SVR_8555) { 682 puts("256 KiB "); 683 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 684 cache_ctl = 0xc8000000; 685 } else { 686 puts("512 KiB "); 687 /* set L2E=1, L2I=1, & L2SRAM=0 */ 688 cache_ctl = 0xc0000000; 689 } 690 break; 691 case 0x3: 692 puts("1024 KiB "); 693 /* set L2E=1, L2I=1, & L2SRAM=0 */ 694 cache_ctl = 0xc0000000; 695 break; 696 } 697 698 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 699 puts("already enabled"); 700 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 701 u32 l2srbar = l2cache->l2srbar0; 702 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 703 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 704 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 705 l2cache->l2srbar0 = l2srbar; 706 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 707 } 708 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 709 puts("\n"); 710 } else { 711 asm("msync;isync"); 712 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 713 asm("msync;isync"); 714 puts("enabled\n"); 715 } 716 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 717 if (SVR_SOC_VER(svr) == SVR_P2040) { 718 puts("N/A\n"); 719 goto skip_l2; 720 } 721 722 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 723 724 /* invalidate the L2 cache */ 725 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 726 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 727 ; 728 729 #ifdef CONFIG_SYS_CACHE_STASHING 730 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 731 mtspr(SPRN_L2CSR1, (32 + 1)); 732 #endif 733 734 /* enable the cache */ 735 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 736 737 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 738 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 739 ; 740 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 741 } 742 743 skip_l2: 744 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 745 if (l2cache->l2csr0 & L2CSR0_L2E) 746 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 747 " enabled\n"); 748 749 enable_cluster_l2(); 750 #else 751 puts("disabled\n"); 752 #endif 753 754 #if defined(CONFIG_RAMBOOT_PBL) 755 disable_cpc_sram(); 756 #endif 757 enable_cpc(); 758 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 759 enable_tdm_law(); 760 #endif 761 762 #ifndef CONFIG_SYS_FSL_NO_SERDES 763 /* needs to be in ram since code uses global static vars */ 764 fsl_serdes_init(); 765 #endif 766 767 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 768 #define MCFGR_AXIPIPE 0x000000f0 769 if (IS_SVR_REV(svr, 1, 0)) 770 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); 771 #endif 772 773 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 774 if (IS_SVR_REV(svr, 1, 0)) { 775 int i; 776 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 777 778 for (i = 0; i < 12; i++) { 779 p += i + (i > 5 ? 11 : 0); 780 out_be32(p, 0x2); 781 } 782 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 783 out_be32(p, 0x34); 784 } 785 #endif 786 787 #ifdef CONFIG_SYS_SRIO 788 srio_init(); 789 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 790 char *s = getenv("bootmaster"); 791 if (s) { 792 if (!strcmp(s, "SRIO1")) { 793 srio_boot_master(1); 794 srio_boot_master_release_slave(1); 795 } 796 if (!strcmp(s, "SRIO2")) { 797 srio_boot_master(2); 798 srio_boot_master_release_slave(2); 799 } 800 } 801 #endif 802 #endif 803 804 #if defined(CONFIG_MP) 805 setup_mp(); 806 #endif 807 808 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 809 { 810 if (SVR_MAJ(svr) < 3) { 811 void *p; 812 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 813 setbits_be32(p, 1 << (31 - 14)); 814 } 815 } 816 #endif 817 818 #ifdef CONFIG_SYS_LBC_LCRR 819 /* 820 * Modify the CLKDIV field of LCRR register to improve the writing 821 * speed for NOR flash. 822 */ 823 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 824 __raw_readl(&lbc->lcrr); 825 isync(); 826 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 827 udelay(100); 828 #endif 829 #endif 830 831 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 832 { 833 struct ccsr_usb_phy __iomem *usb_phy1 = 834 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 835 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 836 if (has_erratum_a006261()) 837 fsl_erratum_a006261_workaround(usb_phy1); 838 #endif 839 out_be32(&usb_phy1->usb_enable_override, 840 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 841 } 842 #endif 843 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 844 { 845 struct ccsr_usb_phy __iomem *usb_phy2 = 846 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 847 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 848 if (has_erratum_a006261()) 849 fsl_erratum_a006261_workaround(usb_phy2); 850 #endif 851 out_be32(&usb_phy2->usb_enable_override, 852 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 853 } 854 #endif 855 856 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 857 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 858 * multi-bit ECC errors which has impact on performance, so software 859 * should disable all ECC reporting from USB1 and USB2. 860 */ 861 if (IS_SVR_REV(get_svr(), 1, 0)) { 862 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 863 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 864 setbits_be32(&dcfg->ecccr1, 865 (DCSR_DCFG_ECC_DISABLE_USB1 | 866 DCSR_DCFG_ECC_DISABLE_USB2)); 867 } 868 #endif 869 870 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 871 struct ccsr_usb_phy __iomem *usb_phy = 872 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 873 setbits_be32(&usb_phy->pllprg[1], 874 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 875 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 876 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 877 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 878 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 879 usb_single_source_clk_configure(usb_phy); 880 #endif 881 setbits_be32(&usb_phy->port1.ctrl, 882 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 883 setbits_be32(&usb_phy->port1.drvvbuscfg, 884 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 885 setbits_be32(&usb_phy->port1.pwrfltcfg, 886 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 887 setbits_be32(&usb_phy->port2.ctrl, 888 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 889 setbits_be32(&usb_phy->port2.drvvbuscfg, 890 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 891 setbits_be32(&usb_phy->port2.pwrfltcfg, 892 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 893 894 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 895 if (has_erratum_a006261()) 896 fsl_erratum_a006261_workaround(usb_phy); 897 #endif 898 899 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ 900 901 #ifdef CONFIG_FMAN_ENET 902 fman_enet_init(); 903 #endif 904 905 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 906 /* 907 * For P1022/1013 Rev1.0 silicon, after power on SATA host 908 * controller is configured in legacy mode instead of the 909 * expected enterprise mode. Software needs to clear bit[28] 910 * of HControl register to change to enterprise mode from 911 * legacy mode. We assume that the controller is offline. 912 */ 913 if (IS_SVR_REV(svr, 1, 0) && 914 ((SVR_SOC_VER(svr) == SVR_P1022) || 915 (SVR_SOC_VER(svr) == SVR_P1013))) { 916 fsl_sata_reg_t *reg; 917 918 /* first SATA controller */ 919 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 920 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 921 922 /* second SATA controller */ 923 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 924 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 925 } 926 #endif 927 928 init_used_tlb_cams(); 929 930 return 0; 931 } 932 933 void arch_preboot_os(void) 934 { 935 u32 msr; 936 937 /* 938 * We are changing interrupt offsets and are about to boot the OS so 939 * we need to make sure we disable all async interrupts. EE is already 940 * disabled by the time we get called. 941 */ 942 msr = mfmsr(); 943 msr &= ~(MSR_ME|MSR_CE); 944 mtmsr(msr); 945 } 946 947 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 948 int sata_initialize(void) 949 { 950 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 951 return __sata_initialize(); 952 953 return 1; 954 } 955 #endif 956 957 void cpu_secondary_init_r(void) 958 { 959 #ifdef CONFIG_U_QE 960 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ 961 #elif defined CONFIG_QE 962 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 963 #endif 964 965 #ifdef CONFIG_QE 966 qe_init(qe_base); 967 qe_reset(); 968 #endif 969 } 970