1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <asm/fsl_law.h> 23 #include <asm/fsl_serdes.h> 24 #include <asm/fsl_srio.h> 25 #include <fsl_usb.h> 26 #include <hwconfig.h> 27 #include <linux/compiler.h> 28 #include "mp.h" 29 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 30 #include <nand.h> 31 #include <errno.h> 32 #endif 33 34 #include "../../../../drivers/block/fsl_sata.h" 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #ifdef CONFIG_QE 39 extern qe_iop_conf_t qe_iop_conf_tab[]; 40 extern void qe_config_iopin(u8 port, u8 pin, int dir, 41 int open_drain, int assign); 42 extern void qe_init(uint qe_base); 43 extern void qe_reset(void); 44 45 static void config_qe_ioports(void) 46 { 47 u8 port, pin; 48 int dir, open_drain, assign; 49 int i; 50 51 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 52 port = qe_iop_conf_tab[i].port; 53 pin = qe_iop_conf_tab[i].pin; 54 dir = qe_iop_conf_tab[i].dir; 55 open_drain = qe_iop_conf_tab[i].open_drain; 56 assign = qe_iop_conf_tab[i].assign; 57 qe_config_iopin(port, pin, dir, open_drain, assign); 58 } 59 } 60 #endif 61 62 #ifdef CONFIG_CPM2 63 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 64 { 65 int portnum; 66 67 for (portnum = 0; portnum < 4; portnum++) { 68 uint pmsk = 0, 69 ppar = 0, 70 psor = 0, 71 pdir = 0, 72 podr = 0, 73 pdat = 0; 74 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 75 iop_conf_t *eiopc = iopc + 32; 76 uint msk = 1; 77 78 /* 79 * NOTE: 80 * index 0 refers to pin 31, 81 * index 31 refers to pin 0 82 */ 83 while (iopc < eiopc) { 84 if (iopc->conf) { 85 pmsk |= msk; 86 if (iopc->ppar) 87 ppar |= msk; 88 if (iopc->psor) 89 psor |= msk; 90 if (iopc->pdir) 91 pdir |= msk; 92 if (iopc->podr) 93 podr |= msk; 94 if (iopc->pdat) 95 pdat |= msk; 96 } 97 98 msk <<= 1; 99 iopc++; 100 } 101 102 if (pmsk != 0) { 103 volatile ioport_t *iop = ioport_addr (cpm, portnum); 104 uint tpmsk = ~pmsk; 105 106 /* 107 * the (somewhat confused) paragraph at the 108 * bottom of page 35-5 warns that there might 109 * be "unknown behaviour" when programming 110 * PSORx and PDIRx, if PPARx = 1, so I 111 * decided this meant I had to disable the 112 * dedicated function first, and enable it 113 * last. 114 */ 115 iop->ppar &= tpmsk; 116 iop->psor = (iop->psor & tpmsk) | psor; 117 iop->podr = (iop->podr & tpmsk) | podr; 118 iop->pdat = (iop->pdat & tpmsk) | pdat; 119 iop->pdir = (iop->pdir & tpmsk) | pdir; 120 iop->ppar |= ppar; 121 } 122 } 123 } 124 #endif 125 126 #ifdef CONFIG_SYS_FSL_CPC 127 static void enable_cpc(void) 128 { 129 int i; 130 u32 size = 0; 131 132 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 133 134 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 135 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 136 size += CPC_CFG0_SZ_K(cpccfg0); 137 #ifdef CONFIG_RAMBOOT_PBL 138 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 139 /* find and disable LAW of SRAM */ 140 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 141 142 if (law.index == -1) { 143 printf("\nFatal error happened\n"); 144 return; 145 } 146 disable_law(law.index); 147 148 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 149 out_be32(&cpc->cpccsr0, 0); 150 out_be32(&cpc->cpcsrcr0, 0); 151 } 152 #endif 153 154 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 155 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 156 #endif 157 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 158 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 159 #endif 160 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 161 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 162 #endif 163 164 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 165 /* Read back to sync write */ 166 in_be32(&cpc->cpccsr0); 167 168 } 169 170 printf("Corenet Platform Cache: %d KB enabled\n", size); 171 } 172 173 static void invalidate_cpc(void) 174 { 175 int i; 176 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 177 178 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 179 /* skip CPC when it used as all SRAM */ 180 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 181 continue; 182 /* Flash invalidate the CPC and clear all the locks */ 183 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 184 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 185 ; 186 } 187 } 188 #else 189 #define enable_cpc() 190 #define invalidate_cpc() 191 #endif /* CONFIG_SYS_FSL_CPC */ 192 193 /* 194 * Breathe some life into the CPU... 195 * 196 * Set up the memory map 197 * initialize a bunch of registers 198 */ 199 200 #ifdef CONFIG_FSL_CORENET 201 static void corenet_tb_init(void) 202 { 203 volatile ccsr_rcpm_t *rcpm = 204 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 205 volatile ccsr_pic_t *pic = 206 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 207 u32 whoami = in_be32(&pic->whoami); 208 209 /* Enable the timebase register for this core */ 210 out_be32(&rcpm->ctbenrl, (1 << whoami)); 211 } 212 #endif 213 214 void cpu_init_f (void) 215 { 216 extern void m8560_cpm_reset (void); 217 #ifdef CONFIG_SYS_DCSRBAR_PHYS 218 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 219 #endif 220 #if defined(CONFIG_SECURE_BOOT) 221 struct law_entry law; 222 #endif 223 #ifdef CONFIG_MPC8548 224 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 225 uint svr = get_svr(); 226 227 /* 228 * CPU2 errata workaround: A core hang possible while executing 229 * a msync instruction and a snoopable transaction from an I/O 230 * master tagged to make quick forward progress is present. 231 * Fixed in silicon rev 2.1. 232 */ 233 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 234 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 235 #endif 236 237 disable_tlb(14); 238 disable_tlb(15); 239 240 #if defined(CONFIG_SECURE_BOOT) 241 /* Disable the LAW created for NOR flash by the PBI commands */ 242 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 243 if (law.index != -1) 244 disable_law(law.index); 245 #endif 246 247 #ifdef CONFIG_CPM2 248 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 249 #endif 250 251 init_early_memctl_regs(); 252 253 #if defined(CONFIG_CPM2) 254 m8560_cpm_reset(); 255 #endif 256 #ifdef CONFIG_QE 257 /* Config QE ioports */ 258 config_qe_ioports(); 259 #endif 260 #if defined(CONFIG_FSL_DMA) 261 dma_init(); 262 #endif 263 #ifdef CONFIG_FSL_CORENET 264 corenet_tb_init(); 265 #endif 266 init_used_tlb_cams(); 267 268 /* Invalidate the CPC before DDR gets enabled */ 269 invalidate_cpc(); 270 271 #ifdef CONFIG_SYS_DCSRBAR_PHYS 272 /* set DCSRCR so that DCSR space is 1G */ 273 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 274 in_be32(&gur->dcsrcr); 275 #endif 276 277 } 278 279 /* Implement a dummy function for those platforms w/o SERDES */ 280 static void __fsl_serdes__init(void) 281 { 282 return ; 283 } 284 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 285 286 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 287 int enable_cluster_l2(void) 288 { 289 int i = 0; 290 u32 cluster; 291 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 292 struct ccsr_cluster_l2 __iomem *l2cache; 293 294 cluster = in_be32(&gur->tp_cluster[i].lower); 295 if (cluster & TP_CLUSTER_EOC) 296 return 0; 297 298 /* The first cache has already been set up, so skip it */ 299 i++; 300 301 /* Look through the remaining clusters, and set up their caches */ 302 do { 303 int j, cluster_valid = 0; 304 305 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 306 307 cluster = in_be32(&gur->tp_cluster[i].lower); 308 309 /* check that at least one core/accel is enabled in cluster */ 310 for (j = 0; j < 4; j++) { 311 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 312 u32 type = in_be32(&gur->tp_ityp[idx]); 313 314 if (type & TP_ITYP_AV) 315 cluster_valid = 1; 316 } 317 318 if (cluster_valid) { 319 /* set stash ID to (cluster) * 2 + 32 + 1 */ 320 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 321 322 printf("enable l2 for cluster %d %p\n", i, l2cache); 323 324 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 325 while ((in_be32(&l2cache->l2csr0) 326 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 327 ; 328 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 329 } 330 i++; 331 } while (!(cluster & TP_CLUSTER_EOC)); 332 333 return 0; 334 } 335 #endif 336 337 /* 338 * Initialize L2 as cache. 339 * 340 * The newer 8548, etc, parts have twice as much cache, but 341 * use the same bit-encoding as the older 8555, etc, parts. 342 * 343 */ 344 int cpu_init_r(void) 345 { 346 __maybe_unused u32 svr = get_svr(); 347 #ifdef CONFIG_SYS_LBC_LCRR 348 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 349 #endif 350 #ifdef CONFIG_L2_CACHE 351 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 352 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 353 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 354 #endif 355 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 356 extern int spin_table_compat; 357 const char *spin; 358 #endif 359 360 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 361 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 362 /* 363 * CPU22 and NMG_CPU_A011 share the same workaround. 364 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 365 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 366 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 367 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 368 * be disabled by hwconfig with syntax: 369 * 370 * fsl_cpu_a011:disable 371 */ 372 extern int enable_cpu_a011_workaround; 373 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 374 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 375 #else 376 char buffer[HWCONFIG_BUFFER_SIZE]; 377 char *buf = NULL; 378 int n, res; 379 380 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 381 if (n > 0) 382 buf = buffer; 383 384 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 385 if (res > 0) 386 enable_cpu_a011_workaround = 0; 387 else { 388 if (n >= HWCONFIG_BUFFER_SIZE) { 389 printf("fsl_cpu_a011 was not found. hwconfig variable " 390 "may be too long\n"); 391 } 392 enable_cpu_a011_workaround = 393 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 394 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 395 } 396 #endif 397 if (enable_cpu_a011_workaround) { 398 flush_dcache(); 399 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 400 sync(); 401 } 402 #endif 403 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 404 /* 405 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 406 * in write shadow mode. Checking DCWS before setting SPR 976. 407 */ 408 if (mfspr(L1CSR2) & L1CSR2_DCWS) 409 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 410 #endif 411 412 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 413 spin = getenv("spin_table_compat"); 414 if (spin && (*spin == 'n')) 415 spin_table_compat = 0; 416 else 417 spin_table_compat = 1; 418 #endif 419 420 puts ("L2: "); 421 422 #if defined(CONFIG_L2_CACHE) 423 volatile uint cache_ctl; 424 uint ver; 425 u32 l2siz_field; 426 427 ver = SVR_SOC_VER(svr); 428 429 asm("msync;isync"); 430 cache_ctl = l2cache->l2ctl; 431 432 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 433 if (cache_ctl & MPC85xx_L2CTL_L2E) { 434 /* Clear L2 SRAM memory-mapped base address */ 435 out_be32(&l2cache->l2srbar0, 0x0); 436 out_be32(&l2cache->l2srbar1, 0x0); 437 438 /* set MBECCDIS=0, SBECCDIS=0 */ 439 clrbits_be32(&l2cache->l2errdis, 440 (MPC85xx_L2ERRDIS_MBECC | 441 MPC85xx_L2ERRDIS_SBECC)); 442 443 /* set L2E=0, L2SRAM=0 */ 444 clrbits_be32(&l2cache->l2ctl, 445 (MPC85xx_L2CTL_L2E | 446 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 447 } 448 #endif 449 450 l2siz_field = (cache_ctl >> 28) & 0x3; 451 452 switch (l2siz_field) { 453 case 0x0: 454 printf(" unknown size (0x%08x)\n", cache_ctl); 455 return -1; 456 break; 457 case 0x1: 458 if (ver == SVR_8540 || ver == SVR_8560 || 459 ver == SVR_8541 || ver == SVR_8555) { 460 puts("128 KB "); 461 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 462 cache_ctl = 0xc4000000; 463 } else { 464 puts("256 KB "); 465 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 466 } 467 break; 468 case 0x2: 469 if (ver == SVR_8540 || ver == SVR_8560 || 470 ver == SVR_8541 || ver == SVR_8555) { 471 puts("256 KB "); 472 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 473 cache_ctl = 0xc8000000; 474 } else { 475 puts ("512 KB "); 476 /* set L2E=1, L2I=1, & L2SRAM=0 */ 477 cache_ctl = 0xc0000000; 478 } 479 break; 480 case 0x3: 481 puts("1024 KB "); 482 /* set L2E=1, L2I=1, & L2SRAM=0 */ 483 cache_ctl = 0xc0000000; 484 break; 485 } 486 487 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 488 puts("already enabled"); 489 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 490 u32 l2srbar = l2cache->l2srbar0; 491 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 492 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 493 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 494 l2cache->l2srbar0 = l2srbar; 495 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 496 } 497 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 498 puts("\n"); 499 } else { 500 asm("msync;isync"); 501 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 502 asm("msync;isync"); 503 puts("enabled\n"); 504 } 505 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 506 if (SVR_SOC_VER(svr) == SVR_P2040) { 507 puts("N/A\n"); 508 goto skip_l2; 509 } 510 511 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 512 513 /* invalidate the L2 cache */ 514 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 515 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 516 ; 517 518 #ifdef CONFIG_SYS_CACHE_STASHING 519 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 520 mtspr(SPRN_L2CSR1, (32 + 1)); 521 #endif 522 523 /* enable the cache */ 524 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 525 526 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 527 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 528 ; 529 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 530 } 531 532 skip_l2: 533 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 534 if (l2cache->l2csr0 & L2CSR0_L2E) 535 printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64); 536 537 enable_cluster_l2(); 538 #else 539 puts("disabled\n"); 540 #endif 541 542 enable_cpc(); 543 544 #ifndef CONFIG_SYS_FSL_NO_SERDES 545 /* needs to be in ram since code uses global static vars */ 546 fsl_serdes_init(); 547 #endif 548 549 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 550 if (IS_SVR_REV(svr, 1, 0)) { 551 int i; 552 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 553 554 for (i = 0; i < 12; i++) { 555 p += i + (i > 5 ? 11 : 0); 556 out_be32(p, 0x2); 557 } 558 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 559 out_be32(p, 0x34); 560 } 561 #endif 562 563 #ifdef CONFIG_SYS_SRIO 564 srio_init(); 565 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 566 char *s = getenv("bootmaster"); 567 if (s) { 568 if (!strcmp(s, "SRIO1")) { 569 srio_boot_master(1); 570 srio_boot_master_release_slave(1); 571 } 572 if (!strcmp(s, "SRIO2")) { 573 srio_boot_master(2); 574 srio_boot_master_release_slave(2); 575 } 576 } 577 #endif 578 #endif 579 580 #if defined(CONFIG_MP) 581 setup_mp(); 582 #endif 583 584 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 585 { 586 if (SVR_MAJ(svr) < 3) { 587 void *p; 588 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 589 setbits_be32(p, 1 << (31 - 14)); 590 } 591 } 592 #endif 593 594 #ifdef CONFIG_SYS_LBC_LCRR 595 /* 596 * Modify the CLKDIV field of LCRR register to improve the writing 597 * speed for NOR flash. 598 */ 599 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 600 __raw_readl(&lbc->lcrr); 601 isync(); 602 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 603 udelay(100); 604 #endif 605 #endif 606 607 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 608 { 609 struct ccsr_usb_phy __iomem *usb_phy1 = 610 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 611 out_be32(&usb_phy1->usb_enable_override, 612 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 613 } 614 #endif 615 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 616 { 617 struct ccsr_usb_phy __iomem *usb_phy2 = 618 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 619 out_be32(&usb_phy2->usb_enable_override, 620 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 621 } 622 #endif 623 624 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 625 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 626 * multi-bit ECC errors which has impact on performance, so software 627 * should disable all ECC reporting from USB1 and USB2. 628 */ 629 if (IS_SVR_REV(get_svr(), 1, 0)) { 630 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 631 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 632 setbits_be32(&dcfg->ecccr1, 633 (DCSR_DCFG_ECC_DISABLE_USB1 | 634 DCSR_DCFG_ECC_DISABLE_USB2)); 635 } 636 #endif 637 638 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 639 struct ccsr_usb_phy __iomem *usb_phy = 640 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 641 setbits_be32(&usb_phy->pllprg[1], 642 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 643 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 644 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 645 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 646 setbits_be32(&usb_phy->port1.ctrl, 647 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 648 setbits_be32(&usb_phy->port1.drvvbuscfg, 649 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 650 setbits_be32(&usb_phy->port1.pwrfltcfg, 651 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 652 setbits_be32(&usb_phy->port2.ctrl, 653 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 654 setbits_be32(&usb_phy->port2.drvvbuscfg, 655 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 656 setbits_be32(&usb_phy->port2.pwrfltcfg, 657 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 658 #endif 659 660 #ifdef CONFIG_FMAN_ENET 661 fman_enet_init(); 662 #endif 663 664 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 665 /* 666 * For P1022/1013 Rev1.0 silicon, after power on SATA host 667 * controller is configured in legacy mode instead of the 668 * expected enterprise mode. Software needs to clear bit[28] 669 * of HControl register to change to enterprise mode from 670 * legacy mode. We assume that the controller is offline. 671 */ 672 if (IS_SVR_REV(svr, 1, 0) && 673 ((SVR_SOC_VER(svr) == SVR_P1022) || 674 (SVR_SOC_VER(svr) == SVR_P1013))) { 675 fsl_sata_reg_t *reg; 676 677 /* first SATA controller */ 678 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 679 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 680 681 /* second SATA controller */ 682 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 683 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 684 } 685 #endif 686 687 688 return 0; 689 } 690 691 extern void setup_ivors(void); 692 693 void arch_preboot_os(void) 694 { 695 u32 msr; 696 697 /* 698 * We are changing interrupt offsets and are about to boot the OS so 699 * we need to make sure we disable all async interrupts. EE is already 700 * disabled by the time we get called. 701 */ 702 msr = mfmsr(); 703 msr &= ~(MSR_ME|MSR_CE); 704 mtmsr(msr); 705 706 setup_ivors(); 707 } 708 709 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 710 int sata_initialize(void) 711 { 712 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 713 return __sata_initialize(); 714 715 return 1; 716 } 717 #endif 718 719 void cpu_secondary_init_r(void) 720 { 721 #ifdef CONFIG_QE 722 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 723 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 724 int ret; 725 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; 726 727 /* load QE firmware from NAND flash to DDR first */ 728 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, 729 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); 730 731 if (ret && ret == -EUCLEAN) { 732 printf ("NAND read for QE firmware at offset %x failed %d\n", 733 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); 734 } 735 #endif 736 qe_init(qe_base); 737 qe_reset(); 738 #endif 739 } 740