1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <watchdog.h> 15 #include <command.h> 16 #include <fsl_esdhc.h> 17 #include <asm/cache.h> 18 #include <asm/io.h> 19 #include <asm/mmu.h> 20 #include <fsl_ifc.h> 21 #include <asm/fsl_law.h> 22 #include <asm/fsl_lbc.h> 23 #include <post.h> 24 #include <asm/processor.h> 25 #include <fsl_ddr_sdram.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 /* 30 * Default board reset function 31 */ 32 static void 33 __board_reset(void) 34 { 35 /* Do nothing */ 36 } 37 void board_reset(void) __attribute__((weak, alias("__board_reset"))); 38 39 int checkcpu (void) 40 { 41 sys_info_t sysinfo; 42 uint pvr, svr; 43 uint ver; 44 uint major, minor; 45 struct cpu_type *cpu; 46 char buf1[32], buf2[32]; 47 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 48 ccsr_gur_t __iomem *gur = 49 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50 #endif 51 52 /* 53 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async 54 * mode. Previous platform use ddr ratio to do the same. This 55 * information is only for display here. 56 */ 57 #ifdef CONFIG_FSL_CORENET 58 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 59 u32 ddr_sync = 0; /* only async mode is supported */ 60 #else 61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 63 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 64 #else /* CONFIG_FSL_CORENET */ 65 #ifdef CONFIG_DDR_CLK_FREQ 66 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 67 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 68 #else 69 u32 ddr_ratio = 0; 70 #endif /* CONFIG_DDR_CLK_FREQ */ 71 #endif /* CONFIG_FSL_CORENET */ 72 73 unsigned int i, core, nr_cores = cpu_numcores(); 74 u32 mask = cpu_mask(); 75 76 svr = get_svr(); 77 major = SVR_MAJ(svr); 78 minor = SVR_MIN(svr); 79 80 if (cpu_numcores() > 1) { 81 #ifndef CONFIG_MP 82 puts("Unicore software on multiprocessor system!!\n" 83 "To enable mutlticore build define CONFIG_MP\n"); 84 #endif 85 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 86 printf("CPU%d: ", pic->whoami); 87 } else { 88 puts("CPU: "); 89 } 90 91 cpu = gd->arch.cpu; 92 93 puts(cpu->name); 94 if (IS_E_PROCESSOR(svr)) 95 puts("E"); 96 97 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 98 99 pvr = get_pvr(); 100 ver = PVR_VER(pvr); 101 major = PVR_MAJ(pvr); 102 minor = PVR_MIN(pvr); 103 104 printf("Core: "); 105 switch(ver) { 106 case PVR_VER_E500_V1: 107 case PVR_VER_E500_V2: 108 puts("e500"); 109 break; 110 case PVR_VER_E500MC: 111 puts("e500mc"); 112 break; 113 case PVR_VER_E5500: 114 puts("e5500"); 115 break; 116 case PVR_VER_E6500: 117 puts("e6500"); 118 break; 119 default: 120 puts("Unknown"); 121 break; 122 } 123 124 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 125 126 if (nr_cores > CONFIG_MAX_CPUS) { 127 panic("\nUnexpected number of cores: %d, max is %d\n", 128 nr_cores, CONFIG_MAX_CPUS); 129 } 130 131 get_sys_info(&sysinfo); 132 133 puts("Clock Configuration:"); 134 for_each_cpu(i, core, nr_cores, mask) { 135 if (!(i & 3)) 136 printf ("\n "); 137 printf("CPU%d:%-4s MHz, ", core, 138 strmhz(buf1, sysinfo.freq_processor[core])); 139 } 140 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); 141 printf("\n"); 142 143 #ifdef CONFIG_FSL_CORENET 144 if (ddr_sync == 1) { 145 printf(" DDR:%-4s MHz (%s MT/s data rate) " 146 "(Synchronous), ", 147 strmhz(buf1, sysinfo.freq_ddrbus/2), 148 strmhz(buf2, sysinfo.freq_ddrbus)); 149 } else { 150 printf(" DDR:%-4s MHz (%s MT/s data rate) " 151 "(Asynchronous), ", 152 strmhz(buf1, sysinfo.freq_ddrbus/2), 153 strmhz(buf2, sysinfo.freq_ddrbus)); 154 } 155 #else 156 switch (ddr_ratio) { 157 case 0x0: 158 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 159 strmhz(buf1, sysinfo.freq_ddrbus/2), 160 strmhz(buf2, sysinfo.freq_ddrbus)); 161 break; 162 case 0x7: 163 printf(" DDR:%-4s MHz (%s MT/s data rate) " 164 "(Synchronous), ", 165 strmhz(buf1, sysinfo.freq_ddrbus/2), 166 strmhz(buf2, sysinfo.freq_ddrbus)); 167 break; 168 default: 169 printf(" DDR:%-4s MHz (%s MT/s data rate) " 170 "(Asynchronous), ", 171 strmhz(buf1, sysinfo.freq_ddrbus/2), 172 strmhz(buf2, sysinfo.freq_ddrbus)); 173 break; 174 } 175 #endif 176 177 #if defined(CONFIG_FSL_LBC) 178 if (sysinfo.freq_localbus > LCRR_CLKDIV) { 179 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); 180 } else { 181 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 182 sysinfo.freq_localbus); 183 } 184 #endif 185 186 #if defined(CONFIG_FSL_IFC) 187 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); 188 #endif 189 190 #ifdef CONFIG_CPM2 191 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); 192 #endif 193 194 #ifdef CONFIG_QE 195 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); 196 #endif 197 198 #ifdef CONFIG_SYS_DPAA_FMAN 199 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 200 printf(" FMAN%d: %s MHz\n", i + 1, 201 strmhz(buf1, sysinfo.freq_fman[i])); 202 } 203 #endif 204 205 #ifdef CONFIG_SYS_DPAA_QBMAN 206 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman)); 207 #endif 208 209 #ifdef CONFIG_SYS_DPAA_PME 210 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme)); 211 #endif 212 213 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); 214 215 #ifdef CONFIG_FSL_CORENET 216 /* Display the RCW, so that no one gets confused as to what RCW 217 * we're actually using for this boot. 218 */ 219 puts("Reset Configuration Word (RCW):"); 220 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 221 u32 rcw = in_be32(&gur->rcwsr[i]); 222 223 if ((i % 4) == 0) 224 printf("\n %08x:", i * 4); 225 printf(" %08x", rcw); 226 } 227 puts("\n"); 228 #endif 229 230 return 0; 231 } 232 233 234 /* ------------------------------------------------------------------------- */ 235 236 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 237 { 238 /* Everything after the first generation of PQ3 parts has RSTCR */ 239 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 240 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 241 unsigned long val, msr; 242 243 /* 244 * Initiate hard reset in debug control register DBCR0 245 * Make sure MSR[DE] = 1. This only resets the core. 246 */ 247 msr = mfmsr (); 248 msr |= MSR_DE; 249 mtmsr (msr); 250 251 val = mfspr(DBCR0); 252 val |= 0x70000000; 253 mtspr(DBCR0,val); 254 #else 255 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 256 257 /* Attempt board-specific reset */ 258 board_reset(); 259 260 /* Next try asserting HRESET_REQ */ 261 out_be32(&gur->rstcr, 0x2); 262 udelay(100); 263 #endif 264 265 return 1; 266 } 267 268 269 /* 270 * Get timebase clock frequency 271 */ 272 #ifndef CONFIG_SYS_FSL_TBCLK_DIV 273 #define CONFIG_SYS_FSL_TBCLK_DIV 8 274 #endif 275 __weak unsigned long get_tbclk (void) 276 { 277 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; 278 279 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; 280 } 281 282 283 #if defined(CONFIG_WATCHDOG) 284 void 285 reset_85xx_watchdog(void) 286 { 287 /* 288 * Clear TSR(WIS) bit by writing 1 289 */ 290 mtspr(SPRN_TSR, TSR_WIS); 291 } 292 293 void 294 watchdog_reset(void) 295 { 296 int re_enable = disable_interrupts(); 297 298 reset_85xx_watchdog(); 299 if (re_enable) 300 enable_interrupts(); 301 } 302 #endif /* CONFIG_WATCHDOG */ 303 304 /* 305 * Initializes on-chip MMC controllers. 306 * to override, implement board_mmc_init() 307 */ 308 int cpu_mmc_init(bd_t *bis) 309 { 310 #ifdef CONFIG_FSL_ESDHC 311 return fsl_esdhc_mmc_init(bis); 312 #else 313 return 0; 314 #endif 315 } 316 317 /* 318 * Print out the state of various machine registers. 319 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 320 * parameters for IFC and TLBs 321 */ 322 void mpc85xx_reginfo(void) 323 { 324 print_tlbcam(); 325 print_laws(); 326 #if defined(CONFIG_FSL_LBC) 327 print_lbc_regs(); 328 #endif 329 #ifdef CONFIG_FSL_IFC 330 print_ifc_regs(); 331 #endif 332 333 } 334 335 /* Common ddr init for non-corenet fsl 85xx platforms */ 336 #ifndef CONFIG_FSL_CORENET 337 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ 338 !defined(CONFIG_SYS_INIT_L2_ADDR) 339 phys_size_t initdram(int board_type) 340 { 341 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ 342 defined(CONFIG_QEMU_E500) 343 return fsl_ddr_sdram_size(); 344 #else 345 return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 346 #endif 347 } 348 #else /* CONFIG_SYS_RAMBOOT */ 349 phys_size_t initdram(int board_type) 350 { 351 phys_size_t dram_size = 0; 352 353 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 354 { 355 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 356 unsigned int x = 10; 357 unsigned int i; 358 359 /* 360 * Work around to stabilize DDR DLL 361 */ 362 out_be32(&gur->ddrdllcr, 0x81000000); 363 asm("sync;isync;msync"); 364 udelay(200); 365 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 366 setbits_be32(&gur->devdisr, 0x00010000); 367 for (i = 0; i < x; i++) 368 ; 369 clrbits_be32(&gur->devdisr, 0x00010000); 370 x++; 371 } 372 } 373 #endif 374 375 #if defined(CONFIG_SPD_EEPROM) || \ 376 defined(CONFIG_DDR_SPD) || \ 377 defined(CONFIG_SYS_DDR_RAW_TIMING) 378 dram_size = fsl_ddr_sdram(); 379 #else 380 dram_size = fixed_sdram(); 381 #endif 382 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 383 dram_size *= 0x100000; 384 385 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 386 /* 387 * Initialize and enable DDR ECC. 388 */ 389 ddr_enable_ecc(dram_size); 390 #endif 391 392 #if defined(CONFIG_FSL_LBC) 393 /* Some boards also have sdram on the lbc */ 394 lbc_sdram_init(); 395 #endif 396 397 debug("DDR: "); 398 return dram_size; 399 } 400 #endif /* CONFIG_SYS_RAMBOOT */ 401 #endif 402 403 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 404 405 /* Board-specific functions defined in each board's ddr.c */ 406 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 407 unsigned int ctrl_num); 408 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 409 phys_addr_t *rpn); 410 unsigned int 411 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 412 413 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 414 415 static void dump_spd_ddr_reg(void) 416 { 417 int i, j, k, m; 418 u8 *p_8; 419 u32 *p_32; 420 struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 421 generic_spd_eeprom_t 422 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 423 424 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 425 fsl_ddr_get_spd(spd[i], i); 426 427 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 428 puts("Byte (hex) "); 429 k = 1; 430 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 431 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 432 printf("Dimm%d ", k++); 433 } 434 puts("\n"); 435 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 436 m = 0; 437 printf("%3d (0x%02x) ", k, k); 438 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 439 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 440 p_8 = (u8 *) &spd[i][j]; 441 if (p_8[k]) { 442 printf("0x%02x ", p_8[k]); 443 m++; 444 } else 445 puts(" "); 446 } 447 } 448 if (m) 449 puts("\n"); 450 else 451 puts("\r"); 452 } 453 454 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 455 switch (i) { 456 case 0: 457 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR; 458 break; 459 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 460 case 1: 461 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 462 break; 463 #endif 464 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 465 case 2: 466 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 467 break; 468 #endif 469 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 470 case 3: 471 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 472 break; 473 #endif 474 default: 475 printf("%s unexpected controller number = %u\n", 476 __func__, i); 477 return; 478 } 479 } 480 printf("DDR registers dump for all controllers " 481 "(zero vaule is omitted)...\n"); 482 puts("Offset (hex) "); 483 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 484 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 485 puts("\n"); 486 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) { 487 m = 0; 488 printf("%6d (0x%04x)", k * 4, k * 4); 489 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 490 p_32 = (u32 *) ddr[i]; 491 if (p_32[k]) { 492 printf(" 0x%08x", p_32[k]); 493 m++; 494 } else 495 puts(" "); 496 } 497 if (m) 498 puts("\n"); 499 else 500 puts("\r"); 501 } 502 puts("\n"); 503 } 504 505 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 506 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 507 { 508 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 509 unsigned long epn; 510 u32 tsize, valid, ptr; 511 int ddr_esel; 512 513 clear_ddr_tlbs_phys(p_addr, size>>20); 514 515 /* Setup new tlb to cover the physical address */ 516 setup_ddr_tlbs_phys(p_addr, size>>20); 517 518 ptr = vstart; 519 ddr_esel = find_tlb_idx((void *)ptr, 1); 520 if (ddr_esel != -1) { 521 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 522 } else { 523 printf("TLB error in function %s\n", __func__); 524 return -1; 525 } 526 527 return 0; 528 } 529 530 /* 531 * slide the testing window up to test another area 532 * for 32_bit system, the maximum testable memory is limited to 533 * CONFIG_MAX_MEM_MAPPED 534 */ 535 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 536 { 537 phys_addr_t test_cap, p_addr; 538 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 539 540 #if !defined(CONFIG_PHYS_64BIT) || \ 541 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 542 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 543 test_cap = p_size; 544 #else 545 test_cap = gd->ram_size; 546 #endif 547 p_addr = (*vstart) + (*size) + (*phys_offset); 548 if (p_addr < test_cap - 1) { 549 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 550 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 551 return -1; 552 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 553 *size = (u32) p_size; 554 printf("Testing 0x%08llx - 0x%08llx\n", 555 (u64)(*vstart) + (*phys_offset), 556 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 557 } else 558 return 1; 559 560 return 0; 561 } 562 563 /* initialization for testing area */ 564 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 565 { 566 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 567 568 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 569 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 570 *phys_offset = 0; 571 572 #if !defined(CONFIG_PHYS_64BIT) || \ 573 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 574 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 575 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 576 puts("Cannot test more than "); 577 print_size(CONFIG_MAX_MEM_MAPPED, 578 " without proper 36BIT support.\n"); 579 } 580 #endif 581 printf("Testing 0x%08llx - 0x%08llx\n", 582 (u64)(*vstart) + (*phys_offset), 583 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 584 585 return 0; 586 } 587 588 /* invalid TLBs for DDR and remap as normal after testing */ 589 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 590 { 591 unsigned long epn; 592 u32 tsize, valid, ptr; 593 phys_addr_t rpn = 0; 594 int ddr_esel; 595 596 /* disable the TLBs for this testing */ 597 ptr = *vstart; 598 599 while (ptr < (*vstart) + (*size)) { 600 ddr_esel = find_tlb_idx((void *)ptr, 1); 601 if (ddr_esel != -1) { 602 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 603 disable_tlb(ddr_esel); 604 } 605 ptr += TSIZE_TO_BYTES(tsize); 606 } 607 608 puts("Remap DDR "); 609 setup_ddr_tlbs(gd->ram_size>>20); 610 puts("\n"); 611 612 return 0; 613 } 614 615 void arch_memory_failure_handle(void) 616 { 617 dump_spd_ddr_reg(); 618 } 619 #endif 620