1 /* 2 * Copyright 2004,2007-2010 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_law.h> 37 #include <asm/fsl_lbc.h> 38 #include <post.h> 39 #include <asm/processor.h> 40 #include <asm/fsl_ddr_sdram.h> 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 int checkcpu (void) 45 { 46 sys_info_t sysinfo; 47 uint pvr, svr; 48 uint fam; 49 uint ver; 50 uint major, minor; 51 struct cpu_type *cpu; 52 char buf1[32], buf2[32]; 53 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 54 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 55 #endif /* CONFIG_FSL_CORENET */ 56 #ifdef CONFIG_DDR_CLK_FREQ 57 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 58 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 59 #else 60 #ifdef CONFIG_FSL_CORENET 61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 63 #else 64 u32 ddr_ratio = 0; 65 #endif /* CONFIG_FSL_CORENET */ 66 #endif /* CONFIG_DDR_CLK_FREQ */ 67 int i; 68 69 svr = get_svr(); 70 major = SVR_MAJ(svr); 71 #ifdef CONFIG_MPC8536 72 major &= 0x7; /* the msb of this nibble is a mfg code */ 73 #endif 74 minor = SVR_MIN(svr); 75 76 if (cpu_numcores() > 1) { 77 #ifndef CONFIG_MP 78 puts("Unicore software on multiprocessor system!!\n" 79 "To enable mutlticore build define CONFIG_MP\n"); 80 #endif 81 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 82 printf("CPU%d: ", pic->whoami); 83 } else { 84 puts("CPU: "); 85 } 86 87 cpu = gd->cpu; 88 89 puts(cpu->name); 90 if (IS_E_PROCESSOR(svr)) 91 puts("E"); 92 93 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 94 95 pvr = get_pvr(); 96 fam = PVR_FAM(pvr); 97 ver = PVR_VER(pvr); 98 major = PVR_MAJ(pvr); 99 minor = PVR_MIN(pvr); 100 101 printf("Core: "); 102 if (PVR_FAM(PVR_85xx)) { 103 switch(PVR_MEM(pvr)) { 104 case 0x1: 105 case 0x2: 106 puts("E500"); 107 break; 108 case 0x3: 109 puts("E500MC"); 110 break; 111 case 0x4: 112 puts("E5500"); 113 break; 114 default: 115 puts("Unknown"); 116 break; 117 } 118 } else { 119 puts("Unknown"); 120 } 121 122 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 123 124 get_sys_info(&sysinfo); 125 126 puts("Clock Configuration:"); 127 for (i = 0; i < cpu_numcores(); i++) { 128 if (!(i & 3)) 129 printf ("\n "); 130 printf("CPU%d:%-4s MHz, ", 131 i,strmhz(buf1, sysinfo.freqProcessor[i])); 132 } 133 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 134 135 #ifdef CONFIG_FSL_CORENET 136 if (ddr_sync == 1) { 137 printf(" DDR:%-4s MHz (%s MT/s data rate) " 138 "(Synchronous), ", 139 strmhz(buf1, sysinfo.freqDDRBus/2), 140 strmhz(buf2, sysinfo.freqDDRBus)); 141 } else { 142 printf(" DDR:%-4s MHz (%s MT/s data rate) " 143 "(Asynchronous), ", 144 strmhz(buf1, sysinfo.freqDDRBus/2), 145 strmhz(buf2, sysinfo.freqDDRBus)); 146 } 147 #else 148 switch (ddr_ratio) { 149 case 0x0: 150 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 151 strmhz(buf1, sysinfo.freqDDRBus/2), 152 strmhz(buf2, sysinfo.freqDDRBus)); 153 break; 154 case 0x7: 155 printf(" DDR:%-4s MHz (%s MT/s data rate) " 156 "(Synchronous), ", 157 strmhz(buf1, sysinfo.freqDDRBus/2), 158 strmhz(buf2, sysinfo.freqDDRBus)); 159 break; 160 default: 161 printf(" DDR:%-4s MHz (%s MT/s data rate) " 162 "(Asynchronous), ", 163 strmhz(buf1, sysinfo.freqDDRBus/2), 164 strmhz(buf2, sysinfo.freqDDRBus)); 165 break; 166 } 167 #endif 168 169 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 170 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 171 } else { 172 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 173 sysinfo.freqLocalBus); 174 } 175 176 #ifdef CONFIG_CPM2 177 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 178 #endif 179 180 #ifdef CONFIG_QE 181 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 182 #endif 183 184 #ifdef CONFIG_SYS_DPAA_FMAN 185 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 186 printf(" FMAN%d: %s MHz\n", i + 1, 187 strmhz(buf1, sysinfo.freqFMan[i])); 188 } 189 #endif 190 191 #ifdef CONFIG_SYS_DPAA_PME 192 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 193 #endif 194 195 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 196 197 return 0; 198 } 199 200 201 /* ------------------------------------------------------------------------- */ 202 203 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 204 { 205 /* Everything after the first generation of PQ3 parts has RSTCR */ 206 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 207 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 208 unsigned long val, msr; 209 210 /* 211 * Initiate hard reset in debug control register DBCR0 212 * Make sure MSR[DE] = 1. This only resets the core. 213 */ 214 msr = mfmsr (); 215 msr |= MSR_DE; 216 mtmsr (msr); 217 218 val = mfspr(DBCR0); 219 val |= 0x70000000; 220 mtspr(DBCR0,val); 221 #else 222 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 223 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ 224 udelay(100); 225 #endif 226 227 return 1; 228 } 229 230 231 /* 232 * Get timebase clock frequency 233 */ 234 unsigned long get_tbclk (void) 235 { 236 #ifdef CONFIG_FSL_CORENET 237 return (gd->bus_clk + 8) / 16; 238 #else 239 return (gd->bus_clk + 4UL)/8UL; 240 #endif 241 } 242 243 244 #if defined(CONFIG_WATCHDOG) 245 void 246 watchdog_reset(void) 247 { 248 int re_enable = disable_interrupts(); 249 reset_85xx_watchdog(); 250 if (re_enable) enable_interrupts(); 251 } 252 253 void 254 reset_85xx_watchdog(void) 255 { 256 /* 257 * Clear TSR(WIS) bit by writing 1 258 */ 259 unsigned long val; 260 val = mfspr(SPRN_TSR); 261 val |= TSR_WIS; 262 mtspr(SPRN_TSR, val); 263 } 264 #endif /* CONFIG_WATCHDOG */ 265 266 /* 267 * Initializes on-chip MMC controllers. 268 * to override, implement board_mmc_init() 269 */ 270 int cpu_mmc_init(bd_t *bis) 271 { 272 #ifdef CONFIG_FSL_ESDHC 273 return fsl_esdhc_mmc_init(bis); 274 #else 275 return 0; 276 #endif 277 } 278 279 /* 280 * Print out the state of various machine registers. 281 * Currently prints out LAWs, BR0/OR0, and TLBs 282 */ 283 void mpc85xx_reginfo(void) 284 { 285 print_tlbcam(); 286 print_laws(); 287 print_lbc_regs(); 288 } 289 290 /* Common ddr init for non-corenet fsl 85xx platforms */ 291 #ifndef CONFIG_FSL_CORENET 292 phys_size_t initdram(int board_type) 293 { 294 phys_size_t dram_size = 0; 295 296 #if defined(CONFIG_DDR_DLL) 297 { 298 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 299 unsigned int x = 10; 300 unsigned int i; 301 302 /* 303 * Work around to stabilize DDR DLL 304 */ 305 out_be32(&gur->ddrdllcr, 0x81000000); 306 asm("sync;isync;msync"); 307 udelay(200); 308 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 309 setbits_be32(&gur->devdisr, 0x00010000); 310 for (i = 0; i < x; i++) 311 ; 312 clrbits_be32(&gur->devdisr, 0x00010000); 313 x++; 314 } 315 } 316 #endif 317 318 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 319 dram_size = fsl_ddr_sdram(); 320 #else 321 dram_size = fixed_sdram(); 322 #endif 323 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 324 dram_size *= 0x100000; 325 326 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 327 /* 328 * Initialize and enable DDR ECC. 329 */ 330 ddr_enable_ecc(dram_size); 331 #endif 332 333 /* Some boards also have sdram on the lbc */ 334 lbc_sdram_init(); 335 336 puts("DDR: "); 337 return dram_size; 338 } 339 #endif 340 341 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 342 343 /* Board-specific functions defined in each board's ddr.c */ 344 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 345 unsigned int ctrl_num); 346 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 347 phys_addr_t *rpn); 348 unsigned int 349 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 350 351 static void dump_spd_ddr_reg(void) 352 { 353 int i, j, k, m; 354 u8 *p_8; 355 u32 *p_32; 356 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 357 generic_spd_eeprom_t 358 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 359 360 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 361 fsl_ddr_get_spd(spd[i], i); 362 363 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 364 puts("Byte (hex) "); 365 k = 1; 366 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 367 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 368 printf("Dimm%d ", k++); 369 } 370 puts("\n"); 371 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 372 m = 0; 373 printf("%3d (0x%02x) ", k, k); 374 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 375 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 376 p_8 = (u8 *) &spd[i][j]; 377 if (p_8[k]) { 378 printf("0x%02x ", p_8[k]); 379 m++; 380 } else 381 puts(" "); 382 } 383 } 384 if (m) 385 puts("\n"); 386 else 387 puts("\r"); 388 } 389 390 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 391 switch (i) { 392 case 0: 393 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 394 break; 395 #ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR 396 case 1: 397 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 398 break; 399 #endif 400 default: 401 printf("%s unexpected controller number = %u\n", 402 __func__, i); 403 return; 404 } 405 } 406 printf("DDR registers dump for all controllers " 407 "(zero vaule is omitted)...\n"); 408 puts("Offset (hex) "); 409 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 410 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 411 puts("\n"); 412 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 413 m = 0; 414 printf("%6d (0x%04x)", k * 4, k * 4); 415 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 416 p_32 = (u32 *) ddr[i]; 417 if (p_32[k]) { 418 printf(" 0x%08x", p_32[k]); 419 m++; 420 } else 421 puts(" "); 422 } 423 if (m) 424 puts("\n"); 425 else 426 puts("\r"); 427 } 428 puts("\n"); 429 } 430 431 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 432 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 433 { 434 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 435 unsigned long epn; 436 u32 tsize, valid, ptr; 437 phys_addr_t rpn = 0; 438 int ddr_esel; 439 440 ptr = vstart; 441 442 while (ptr < (vstart + size)) { 443 ddr_esel = find_tlb_idx((void *)ptr, 1); 444 if (ddr_esel != -1) { 445 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 446 disable_tlb(ddr_esel); 447 } 448 ptr += TSIZE_TO_BYTES(tsize); 449 } 450 451 /* Setup new tlb to cover the physical address */ 452 setup_ddr_tlbs_phys(p_addr, size>>20); 453 454 ptr = vstart; 455 ddr_esel = find_tlb_idx((void *)ptr, 1); 456 if (ddr_esel != -1) { 457 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 458 } else { 459 printf("TLB error in function %s\n", __func__); 460 return -1; 461 } 462 463 return 0; 464 } 465 466 /* 467 * slide the testing window up to test another area 468 * for 32_bit system, the maximum testable memory is limited to 469 * CONFIG_MAX_MEM_MAPPED 470 */ 471 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 472 { 473 phys_addr_t test_cap, p_addr; 474 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 475 476 #if !defined(CONFIG_PHYS_64BIT) || \ 477 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 478 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 479 test_cap = p_size; 480 #else 481 test_cap = gd->ram_size; 482 #endif 483 p_addr = (*vstart) + (*size) + (*phys_offset); 484 if (p_addr < test_cap - 1) { 485 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 486 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 487 return -1; 488 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 489 *size = (u32) p_size; 490 printf("Testing 0x%08llx - 0x%08llx\n", 491 (u64)(*vstart) + (*phys_offset), 492 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 493 } else 494 return 1; 495 496 return 0; 497 } 498 499 /* initialization for testing area */ 500 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 501 { 502 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 503 504 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 505 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 506 *phys_offset = 0; 507 508 #if !defined(CONFIG_PHYS_64BIT) || \ 509 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 510 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 511 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 512 puts("Cannot test more than "); 513 print_size(CONFIG_MAX_MEM_MAPPED, 514 " without proper 36BIT support.\n"); 515 } 516 #endif 517 printf("Testing 0x%08llx - 0x%08llx\n", 518 (u64)(*vstart) + (*phys_offset), 519 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 520 521 return 0; 522 } 523 524 /* invalid TLBs for DDR and remap as normal after testing */ 525 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 526 { 527 unsigned long epn; 528 u32 tsize, valid, ptr; 529 phys_addr_t rpn = 0; 530 int ddr_esel; 531 532 /* disable the TLBs for this testing */ 533 ptr = *vstart; 534 535 while (ptr < (*vstart) + (*size)) { 536 ddr_esel = find_tlb_idx((void *)ptr, 1); 537 if (ddr_esel != -1) { 538 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 539 disable_tlb(ddr_esel); 540 } 541 ptr += TSIZE_TO_BYTES(tsize); 542 } 543 544 puts("Remap DDR "); 545 setup_ddr_tlbs(gd->ram_size>>20); 546 puts("\n"); 547 548 return 0; 549 } 550 551 void arch_memory_failure_handle(void) 552 { 553 dump_spd_ddr_reg(); 554 } 555 #endif 556