1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7choice 8 prompt "Target select" 9 optional 10 11config TARGET_SBC8548 12 bool "Support sbc8548" 13 select ARCH_MPC8548 14 15config TARGET_SOCRATES 16 bool "Support socrates" 17 select ARCH_MPC8544 18 19config TARGET_B4420QDS 20 bool "Support B4420QDS" 21 select ARCH_B4420 22 select SUPPORT_SPL 23 select PHYS_64BIT 24 25config TARGET_B4860QDS 26 bool "Support B4860QDS" 27 select ARCH_B4860 28 select BOARD_LATE_INIT if CHAIN_OF_TRUST 29 select SUPPORT_SPL 30 select PHYS_64BIT 31 32config TARGET_BSC9131RDB 33 bool "Support BSC9131RDB" 34 select ARCH_BSC9131 35 select SUPPORT_SPL 36 37config TARGET_BSC9132QDS 38 bool "Support BSC9132QDS" 39 select ARCH_BSC9132 40 select BOARD_LATE_INIT if CHAIN_OF_TRUST 41 select SUPPORT_SPL 42 43config TARGET_C29XPCIE 44 bool "Support C29XPCIE" 45 select ARCH_C29X 46 select BOARD_LATE_INIT if CHAIN_OF_TRUST 47 select SUPPORT_SPL 48 select SUPPORT_TPL 49 select PHYS_64BIT 50 51config TARGET_P3041DS 52 bool "Support P3041DS" 53 select PHYS_64BIT 54 select ARCH_P3041 55 select BOARD_LATE_INIT if CHAIN_OF_TRUST 56 57config TARGET_P4080DS 58 bool "Support P4080DS" 59 select PHYS_64BIT 60 select ARCH_P4080 61 select BOARD_LATE_INIT if CHAIN_OF_TRUST 62 63config TARGET_P5020DS 64 bool "Support P5020DS" 65 select PHYS_64BIT 66 select ARCH_P5020 67 select BOARD_LATE_INIT if CHAIN_OF_TRUST 68 69config TARGET_P5040DS 70 bool "Support P5040DS" 71 select PHYS_64BIT 72 select ARCH_P5040 73 select BOARD_LATE_INIT if CHAIN_OF_TRUST 74 75config TARGET_MPC8536DS 76 bool "Support MPC8536DS" 77 select ARCH_MPC8536 78# Use DDR3 controller with DDR2 DIMMs on this board 79 select SYS_FSL_DDRC_GEN3 80 81config TARGET_MPC8540ADS 82 bool "Support MPC8540ADS" 83 select ARCH_MPC8540 84 85config TARGET_MPC8541CDS 86 bool "Support MPC8541CDS" 87 select ARCH_MPC8541 88 89config TARGET_MPC8544DS 90 bool "Support MPC8544DS" 91 select ARCH_MPC8544 92 93config TARGET_MPC8548CDS 94 bool "Support MPC8548CDS" 95 select ARCH_MPC8548 96 97config TARGET_MPC8555CDS 98 bool "Support MPC8555CDS" 99 select ARCH_MPC8555 100 101config TARGET_MPC8560ADS 102 bool "Support MPC8560ADS" 103 select ARCH_MPC8560 104 105config TARGET_MPC8568MDS 106 bool "Support MPC8568MDS" 107 select ARCH_MPC8568 108 109config TARGET_MPC8569MDS 110 bool "Support MPC8569MDS" 111 select ARCH_MPC8569 112 113config TARGET_MPC8572DS 114 bool "Support MPC8572DS" 115 select ARCH_MPC8572 116# Use DDR3 controller with DDR2 DIMMs on this board 117 select SYS_FSL_DDRC_GEN3 118 119config TARGET_P1010RDB_PA 120 bool "Support P1010RDB_PA" 121 select ARCH_P1010 122 select BOARD_LATE_INIT if CHAIN_OF_TRUST 123 select SUPPORT_SPL 124 select SUPPORT_TPL 125 126config TARGET_P1010RDB_PB 127 bool "Support P1010RDB_PB" 128 select ARCH_P1010 129 select BOARD_LATE_INIT if CHAIN_OF_TRUST 130 select SUPPORT_SPL 131 select SUPPORT_TPL 132 133config TARGET_P1022DS 134 bool "Support P1022DS" 135 select ARCH_P1022 136 select SUPPORT_SPL 137 select SUPPORT_TPL 138 139config TARGET_P1023RDB 140 bool "Support P1023RDB" 141 select ARCH_P1023 142 143config TARGET_P1020MBG 144 bool "Support P1020MBG-PC" 145 select SUPPORT_SPL 146 select SUPPORT_TPL 147 select ARCH_P1020 148 149config TARGET_P1020RDB_PC 150 bool "Support P1020RDB-PC" 151 select SUPPORT_SPL 152 select SUPPORT_TPL 153 select ARCH_P1020 154 155config TARGET_P1020RDB_PD 156 bool "Support P1020RDB-PD" 157 select SUPPORT_SPL 158 select SUPPORT_TPL 159 select ARCH_P1020 160 161config TARGET_P1020UTM 162 bool "Support P1020UTM" 163 select SUPPORT_SPL 164 select SUPPORT_TPL 165 select ARCH_P1020 166 167config TARGET_P1021RDB 168 bool "Support P1021RDB" 169 select SUPPORT_SPL 170 select SUPPORT_TPL 171 select ARCH_P1021 172 173config TARGET_P1024RDB 174 bool "Support P1024RDB" 175 select SUPPORT_SPL 176 select SUPPORT_TPL 177 select ARCH_P1024 178 179config TARGET_P1025RDB 180 bool "Support P1025RDB" 181 select SUPPORT_SPL 182 select SUPPORT_TPL 183 select ARCH_P1025 184 185config TARGET_P2020RDB 186 bool "Support P2020RDB-PC" 187 select SUPPORT_SPL 188 select SUPPORT_TPL 189 select ARCH_P2020 190 191config TARGET_P1_TWR 192 bool "Support p1_twr" 193 select ARCH_P1025 194 195config TARGET_P2041RDB 196 bool "Support P2041RDB" 197 select ARCH_P2041 198 select BOARD_LATE_INIT if CHAIN_OF_TRUST 199 select PHYS_64BIT 200 201config TARGET_QEMU_PPCE500 202 bool "Support qemu-ppce500" 203 select ARCH_QEMU_E500 204 select PHYS_64BIT 205 206config TARGET_T1024QDS 207 bool "Support T1024QDS" 208 select ARCH_T1024 209 select BOARD_LATE_INIT if CHAIN_OF_TRUST 210 select SUPPORT_SPL 211 select PHYS_64BIT 212 213config TARGET_T1023RDB 214 bool "Support T1023RDB" 215 select ARCH_T1023 216 select BOARD_LATE_INIT if CHAIN_OF_TRUST 217 select SUPPORT_SPL 218 select PHYS_64BIT 219 220config TARGET_T1024RDB 221 bool "Support T1024RDB" 222 select ARCH_T1024 223 select BOARD_LATE_INIT if CHAIN_OF_TRUST 224 select SUPPORT_SPL 225 select PHYS_64BIT 226 227config TARGET_T1040QDS 228 bool "Support T1040QDS" 229 select ARCH_T1040 230 select BOARD_LATE_INIT if CHAIN_OF_TRUST 231 select PHYS_64BIT 232 233config TARGET_T1040RDB 234 bool "Support T1040RDB" 235 select ARCH_T1040 236 select BOARD_LATE_INIT if CHAIN_OF_TRUST 237 select SUPPORT_SPL 238 select PHYS_64BIT 239 240config TARGET_T1040D4RDB 241 bool "Support T1040D4RDB" 242 select ARCH_T1040 243 select BOARD_LATE_INIT if CHAIN_OF_TRUST 244 select SUPPORT_SPL 245 select PHYS_64BIT 246 247config TARGET_T1042RDB 248 bool "Support T1042RDB" 249 select ARCH_T1042 250 select BOARD_LATE_INIT if CHAIN_OF_TRUST 251 select SUPPORT_SPL 252 select PHYS_64BIT 253 254config TARGET_T1042D4RDB 255 bool "Support T1042D4RDB" 256 select ARCH_T1042 257 select BOARD_LATE_INIT if CHAIN_OF_TRUST 258 select SUPPORT_SPL 259 select PHYS_64BIT 260 261config TARGET_T1042RDB_PI 262 bool "Support T1042RDB_PI" 263 select ARCH_T1042 264 select BOARD_LATE_INIT if CHAIN_OF_TRUST 265 select SUPPORT_SPL 266 select PHYS_64BIT 267 268config TARGET_T2080QDS 269 bool "Support T2080QDS" 270 select ARCH_T2080 271 select BOARD_LATE_INIT if CHAIN_OF_TRUST 272 select SUPPORT_SPL 273 select PHYS_64BIT 274 275config TARGET_T2080RDB 276 bool "Support T2080RDB" 277 select ARCH_T2080 278 select BOARD_LATE_INIT if CHAIN_OF_TRUST 279 select SUPPORT_SPL 280 select PHYS_64BIT 281 282config TARGET_T2081QDS 283 bool "Support T2081QDS" 284 select ARCH_T2081 285 select SUPPORT_SPL 286 select PHYS_64BIT 287 288config TARGET_T4160QDS 289 bool "Support T4160QDS" 290 select ARCH_T4160 291 select BOARD_LATE_INIT if CHAIN_OF_TRUST 292 select SUPPORT_SPL 293 select PHYS_64BIT 294 295config TARGET_T4160RDB 296 bool "Support T4160RDB" 297 select ARCH_T4160 298 select SUPPORT_SPL 299 select PHYS_64BIT 300 301config TARGET_T4240QDS 302 bool "Support T4240QDS" 303 select ARCH_T4240 304 select BOARD_LATE_INIT if CHAIN_OF_TRUST 305 select SUPPORT_SPL 306 select PHYS_64BIT 307 308config TARGET_T4240RDB 309 bool "Support T4240RDB" 310 select ARCH_T4240 311 select SUPPORT_SPL 312 select PHYS_64BIT 313 314config TARGET_CONTROLCENTERD 315 bool "Support controlcenterd" 316 select ARCH_P1022 317 318config TARGET_KMP204X 319 bool "Support kmp204x" 320 select ARCH_P2041 321 select PHYS_64BIT 322 323config TARGET_XPEDITE520X 324 bool "Support xpedite520x" 325 select ARCH_MPC8548 326 327config TARGET_XPEDITE537X 328 bool "Support xpedite537x" 329 select ARCH_MPC8572 330# Use DDR3 controller with DDR2 DIMMs on this board 331 select SYS_FSL_DDRC_GEN3 332 333config TARGET_XPEDITE550X 334 bool "Support xpedite550x" 335 select ARCH_P2020 336 337config TARGET_UCP1020 338 bool "Support uCP1020" 339 select ARCH_P1020 340 341config TARGET_CYRUS_P5020 342 bool "Support Varisys Cyrus P5020" 343 select ARCH_P5020 344 select PHYS_64BIT 345 346config TARGET_CYRUS_P5040 347 bool "Support Varisys Cyrus P5040" 348 select ARCH_P5040 349 select PHYS_64BIT 350 351endchoice 352 353config ARCH_B4420 354 bool 355 select E500MC 356 select E6500 357 select FSL_LAW 358 select SYS_FSL_DDR_VER_47 359 select SYS_FSL_ERRATUM_A004477 360 select SYS_FSL_ERRATUM_A005871 361 select SYS_FSL_ERRATUM_A006379 362 select SYS_FSL_ERRATUM_A006384 363 select SYS_FSL_ERRATUM_A006475 364 select SYS_FSL_ERRATUM_A006593 365 select SYS_FSL_ERRATUM_A007075 366 select SYS_FSL_ERRATUM_A007186 367 select SYS_FSL_ERRATUM_A007212 368 select SYS_FSL_ERRATUM_A009942 369 select SYS_FSL_HAS_DDR3 370 select SYS_FSL_HAS_SEC 371 select SYS_FSL_QORIQ_CHASSIS2 372 select SYS_FSL_SEC_BE 373 select SYS_FSL_SEC_COMPAT_4 374 select SYS_PPC64 375 376config ARCH_B4860 377 bool 378 select E500MC 379 select E6500 380 select FSL_LAW 381 select SYS_FSL_DDR_VER_47 382 select SYS_FSL_ERRATUM_A004477 383 select SYS_FSL_ERRATUM_A005871 384 select SYS_FSL_ERRATUM_A006379 385 select SYS_FSL_ERRATUM_A006384 386 select SYS_FSL_ERRATUM_A006475 387 select SYS_FSL_ERRATUM_A006593 388 select SYS_FSL_ERRATUM_A007075 389 select SYS_FSL_ERRATUM_A007186 390 select SYS_FSL_ERRATUM_A007212 391 select SYS_FSL_ERRATUM_A009942 392 select SYS_FSL_HAS_DDR3 393 select SYS_FSL_HAS_SEC 394 select SYS_FSL_QORIQ_CHASSIS2 395 select SYS_FSL_SEC_BE 396 select SYS_FSL_SEC_COMPAT_4 397 select SYS_PPC64 398 399config ARCH_BSC9131 400 bool 401 select FSL_LAW 402 select SYS_FSL_DDR_VER_44 403 select SYS_FSL_ERRATUM_A004477 404 select SYS_FSL_ERRATUM_A005125 405 select SYS_FSL_ERRATUM_ESDHC111 406 select SYS_FSL_HAS_DDR3 407 select SYS_FSL_HAS_SEC 408 select SYS_FSL_SEC_BE 409 select SYS_FSL_SEC_COMPAT_4 410 411config ARCH_BSC9132 412 bool 413 select FSL_LAW 414 select SYS_FSL_DDR_VER_46 415 select SYS_FSL_ERRATUM_A004477 416 select SYS_FSL_ERRATUM_A005125 417 select SYS_FSL_ERRATUM_A005434 418 select SYS_FSL_ERRATUM_ESDHC111 419 select SYS_FSL_ERRATUM_I2C_A004447 420 select SYS_FSL_ERRATUM_IFC_A002769 421 select SYS_FSL_HAS_DDR3 422 select SYS_FSL_HAS_SEC 423 select SYS_FSL_SEC_BE 424 select SYS_FSL_SEC_COMPAT_4 425 select SYS_PPC_E500_USE_DEBUG_TLB 426 427config ARCH_C29X 428 bool 429 select FSL_LAW 430 select SYS_FSL_DDR_VER_46 431 select SYS_FSL_ERRATUM_A005125 432 select SYS_FSL_ERRATUM_ESDHC111 433 select SYS_FSL_HAS_DDR3 434 select SYS_FSL_HAS_SEC 435 select SYS_FSL_SEC_BE 436 select SYS_FSL_SEC_COMPAT_6 437 select SYS_PPC_E500_USE_DEBUG_TLB 438 439config ARCH_MPC8536 440 bool 441 select FSL_LAW 442 select SYS_FSL_ERRATUM_A004508 443 select SYS_FSL_ERRATUM_A005125 444 select SYS_FSL_HAS_DDR2 445 select SYS_FSL_HAS_DDR3 446 select SYS_FSL_HAS_SEC 447 select SYS_FSL_SEC_BE 448 select SYS_FSL_SEC_COMPAT_2 449 select SYS_PPC_E500_USE_DEBUG_TLB 450 451config ARCH_MPC8540 452 bool 453 select FSL_LAW 454 select SYS_FSL_HAS_DDR1 455 456config ARCH_MPC8541 457 bool 458 select FSL_LAW 459 select SYS_FSL_HAS_DDR1 460 select SYS_FSL_HAS_SEC 461 select SYS_FSL_SEC_BE 462 select SYS_FSL_SEC_COMPAT_2 463 464config ARCH_MPC8544 465 bool 466 select FSL_LAW 467 select SYS_FSL_ERRATUM_A005125 468 select SYS_FSL_HAS_DDR2 469 select SYS_FSL_HAS_SEC 470 select SYS_FSL_SEC_BE 471 select SYS_FSL_SEC_COMPAT_2 472 select SYS_PPC_E500_USE_DEBUG_TLB 473 474config ARCH_MPC8548 475 bool 476 select FSL_LAW 477 select SYS_FSL_ERRATUM_A005125 478 select SYS_FSL_ERRATUM_NMG_DDR120 479 select SYS_FSL_ERRATUM_NMG_LBC103 480 select SYS_FSL_ERRATUM_NMG_ETSEC129 481 select SYS_FSL_ERRATUM_I2C_A004447 482 select SYS_FSL_HAS_DDR2 483 select SYS_FSL_HAS_DDR1 484 select SYS_FSL_HAS_SEC 485 select SYS_FSL_SEC_BE 486 select SYS_FSL_SEC_COMPAT_2 487 select SYS_PPC_E500_USE_DEBUG_TLB 488 489config ARCH_MPC8555 490 bool 491 select FSL_LAW 492 select SYS_FSL_HAS_DDR1 493 select SYS_FSL_HAS_SEC 494 select SYS_FSL_SEC_BE 495 select SYS_FSL_SEC_COMPAT_2 496 497config ARCH_MPC8560 498 bool 499 select FSL_LAW 500 select SYS_FSL_HAS_DDR1 501 502config ARCH_MPC8568 503 bool 504 select FSL_LAW 505 select SYS_FSL_HAS_DDR2 506 select SYS_FSL_HAS_SEC 507 select SYS_FSL_SEC_BE 508 select SYS_FSL_SEC_COMPAT_2 509 510config ARCH_MPC8569 511 bool 512 select FSL_LAW 513 select SYS_FSL_ERRATUM_A004508 514 select SYS_FSL_ERRATUM_A005125 515 select SYS_FSL_HAS_DDR3 516 select SYS_FSL_HAS_SEC 517 select SYS_FSL_SEC_BE 518 select SYS_FSL_SEC_COMPAT_2 519 520config ARCH_MPC8572 521 bool 522 select FSL_LAW 523 select SYS_FSL_ERRATUM_A004508 524 select SYS_FSL_ERRATUM_A005125 525 select SYS_FSL_ERRATUM_DDR_115 526 select SYS_FSL_ERRATUM_DDR111_DDR134 527 select SYS_FSL_HAS_DDR2 528 select SYS_FSL_HAS_DDR3 529 select SYS_FSL_HAS_SEC 530 select SYS_FSL_SEC_BE 531 select SYS_FSL_SEC_COMPAT_2 532 select SYS_PPC_E500_USE_DEBUG_TLB 533 534config ARCH_P1010 535 bool 536 select FSL_LAW 537 select SYS_FSL_ERRATUM_A004477 538 select SYS_FSL_ERRATUM_A004508 539 select SYS_FSL_ERRATUM_A005125 540 select SYS_FSL_ERRATUM_A006261 541 select SYS_FSL_ERRATUM_A007075 542 select SYS_FSL_ERRATUM_ESDHC111 543 select SYS_FSL_ERRATUM_I2C_A004447 544 select SYS_FSL_ERRATUM_IFC_A002769 545 select SYS_FSL_ERRATUM_P1010_A003549 546 select SYS_FSL_ERRATUM_SEC_A003571 547 select SYS_FSL_ERRATUM_IFC_A003399 548 select SYS_FSL_HAS_DDR3 549 select SYS_FSL_HAS_SEC 550 select SYS_FSL_SEC_BE 551 select SYS_FSL_SEC_COMPAT_4 552 select SYS_PPC_E500_USE_DEBUG_TLB 553 554config ARCH_P1011 555 bool 556 select FSL_LAW 557 select SYS_FSL_ERRATUM_A004508 558 select SYS_FSL_ERRATUM_A005125 559 select SYS_FSL_ERRATUM_ELBC_A001 560 select SYS_FSL_ERRATUM_ESDHC111 561 select SYS_FSL_HAS_DDR3 562 select SYS_FSL_HAS_SEC 563 select SYS_FSL_SEC_BE 564 select SYS_FSL_SEC_COMPAT_2 565 select SYS_PPC_E500_USE_DEBUG_TLB 566 567config ARCH_P1020 568 bool 569 select FSL_LAW 570 select SYS_FSL_ERRATUM_A004508 571 select SYS_FSL_ERRATUM_A005125 572 select SYS_FSL_ERRATUM_ELBC_A001 573 select SYS_FSL_ERRATUM_ESDHC111 574 select SYS_FSL_HAS_DDR3 575 select SYS_FSL_HAS_SEC 576 select SYS_FSL_SEC_BE 577 select SYS_FSL_SEC_COMPAT_2 578 select SYS_PPC_E500_USE_DEBUG_TLB 579 580config ARCH_P1021 581 bool 582 select FSL_LAW 583 select SYS_FSL_ERRATUM_A004508 584 select SYS_FSL_ERRATUM_A005125 585 select SYS_FSL_ERRATUM_ELBC_A001 586 select SYS_FSL_ERRATUM_ESDHC111 587 select SYS_FSL_HAS_DDR3 588 select SYS_FSL_HAS_SEC 589 select SYS_FSL_SEC_BE 590 select SYS_FSL_SEC_COMPAT_2 591 select SYS_PPC_E500_USE_DEBUG_TLB 592 593config ARCH_P1022 594 bool 595 select FSL_LAW 596 select SYS_FSL_ERRATUM_A004477 597 select SYS_FSL_ERRATUM_A004508 598 select SYS_FSL_ERRATUM_A005125 599 select SYS_FSL_ERRATUM_ELBC_A001 600 select SYS_FSL_ERRATUM_ESDHC111 601 select SYS_FSL_ERRATUM_SATA_A001 602 select SYS_FSL_HAS_DDR3 603 select SYS_FSL_HAS_SEC 604 select SYS_FSL_SEC_BE 605 select SYS_FSL_SEC_COMPAT_2 606 select SYS_PPC_E500_USE_DEBUG_TLB 607 608config ARCH_P1023 609 bool 610 select FSL_LAW 611 select SYS_FSL_ERRATUM_A004508 612 select SYS_FSL_ERRATUM_A005125 613 select SYS_FSL_ERRATUM_I2C_A004447 614 select SYS_FSL_HAS_DDR3 615 select SYS_FSL_HAS_SEC 616 select SYS_FSL_SEC_BE 617 select SYS_FSL_SEC_COMPAT_4 618 619config ARCH_P1024 620 bool 621 select FSL_LAW 622 select SYS_FSL_ERRATUM_A004508 623 select SYS_FSL_ERRATUM_A005125 624 select SYS_FSL_ERRATUM_ELBC_A001 625 select SYS_FSL_ERRATUM_ESDHC111 626 select SYS_FSL_HAS_DDR3 627 select SYS_FSL_HAS_SEC 628 select SYS_FSL_SEC_BE 629 select SYS_FSL_SEC_COMPAT_2 630 select SYS_PPC_E500_USE_DEBUG_TLB 631 632config ARCH_P1025 633 bool 634 select FSL_LAW 635 select SYS_FSL_ERRATUM_A004508 636 select SYS_FSL_ERRATUM_A005125 637 select SYS_FSL_ERRATUM_ELBC_A001 638 select SYS_FSL_ERRATUM_ESDHC111 639 select SYS_FSL_HAS_DDR3 640 select SYS_FSL_HAS_SEC 641 select SYS_FSL_SEC_BE 642 select SYS_FSL_SEC_COMPAT_2 643 select SYS_PPC_E500_USE_DEBUG_TLB 644 645config ARCH_P2020 646 bool 647 select FSL_LAW 648 select SYS_FSL_ERRATUM_A004477 649 select SYS_FSL_ERRATUM_A004508 650 select SYS_FSL_ERRATUM_A005125 651 select SYS_FSL_ERRATUM_ESDHC111 652 select SYS_FSL_ERRATUM_ESDHC_A001 653 select SYS_FSL_HAS_DDR3 654 select SYS_FSL_HAS_SEC 655 select SYS_FSL_SEC_BE 656 select SYS_FSL_SEC_COMPAT_2 657 select SYS_PPC_E500_USE_DEBUG_TLB 658 659config ARCH_P2041 660 bool 661 select E500MC 662 select FSL_LAW 663 select SYS_FSL_ERRATUM_A004510 664 select SYS_FSL_ERRATUM_A004849 665 select SYS_FSL_ERRATUM_A006261 666 select SYS_FSL_ERRATUM_CPU_A003999 667 select SYS_FSL_ERRATUM_DDR_A003 668 select SYS_FSL_ERRATUM_DDR_A003474 669 select SYS_FSL_ERRATUM_ESDHC111 670 select SYS_FSL_ERRATUM_I2C_A004447 671 select SYS_FSL_ERRATUM_NMG_CPU_A011 672 select SYS_FSL_ERRATUM_SRIO_A004034 673 select SYS_FSL_ERRATUM_USB14 674 select SYS_FSL_HAS_DDR3 675 select SYS_FSL_HAS_SEC 676 select SYS_FSL_QORIQ_CHASSIS1 677 select SYS_FSL_SEC_BE 678 select SYS_FSL_SEC_COMPAT_4 679 680config ARCH_P3041 681 bool 682 select E500MC 683 select FSL_LAW 684 select SYS_FSL_DDR_VER_44 685 select SYS_FSL_ERRATUM_A004510 686 select SYS_FSL_ERRATUM_A004849 687 select SYS_FSL_ERRATUM_A005812 688 select SYS_FSL_ERRATUM_A006261 689 select SYS_FSL_ERRATUM_CPU_A003999 690 select SYS_FSL_ERRATUM_DDR_A003 691 select SYS_FSL_ERRATUM_DDR_A003474 692 select SYS_FSL_ERRATUM_ESDHC111 693 select SYS_FSL_ERRATUM_I2C_A004447 694 select SYS_FSL_ERRATUM_NMG_CPU_A011 695 select SYS_FSL_ERRATUM_SRIO_A004034 696 select SYS_FSL_ERRATUM_USB14 697 select SYS_FSL_HAS_DDR3 698 select SYS_FSL_HAS_SEC 699 select SYS_FSL_QORIQ_CHASSIS1 700 select SYS_FSL_SEC_BE 701 select SYS_FSL_SEC_COMPAT_4 702 703config ARCH_P4080 704 bool 705 select E500MC 706 select FSL_LAW 707 select SYS_FSL_DDR_VER_44 708 select SYS_FSL_ERRATUM_A004510 709 select SYS_FSL_ERRATUM_A004580 710 select SYS_FSL_ERRATUM_A004849 711 select SYS_FSL_ERRATUM_A005812 712 select SYS_FSL_ERRATUM_A007075 713 select SYS_FSL_ERRATUM_CPC_A002 714 select SYS_FSL_ERRATUM_CPC_A003 715 select SYS_FSL_ERRATUM_CPU_A003999 716 select SYS_FSL_ERRATUM_DDR_A003 717 select SYS_FSL_ERRATUM_DDR_A003474 718 select SYS_FSL_ERRATUM_ELBC_A001 719 select SYS_FSL_ERRATUM_ESDHC111 720 select SYS_FSL_ERRATUM_ESDHC13 721 select SYS_FSL_ERRATUM_ESDHC135 722 select SYS_FSL_ERRATUM_I2C_A004447 723 select SYS_FSL_ERRATUM_NMG_CPU_A011 724 select SYS_FSL_ERRATUM_SRIO_A004034 725 select SYS_P4080_ERRATUM_CPU22 726 select SYS_P4080_ERRATUM_PCIE_A003 727 select SYS_P4080_ERRATUM_SERDES8 728 select SYS_P4080_ERRATUM_SERDES9 729 select SYS_P4080_ERRATUM_SERDES_A001 730 select SYS_P4080_ERRATUM_SERDES_A005 731 select SYS_FSL_HAS_DDR3 732 select SYS_FSL_HAS_SEC 733 select SYS_FSL_QORIQ_CHASSIS1 734 select SYS_FSL_SEC_BE 735 select SYS_FSL_SEC_COMPAT_4 736 737config ARCH_P5020 738 bool 739 select E500MC 740 select FSL_LAW 741 select SYS_FSL_DDR_VER_44 742 select SYS_FSL_ERRATUM_A004510 743 select SYS_FSL_ERRATUM_A006261 744 select SYS_FSL_ERRATUM_DDR_A003 745 select SYS_FSL_ERRATUM_DDR_A003474 746 select SYS_FSL_ERRATUM_ESDHC111 747 select SYS_FSL_ERRATUM_I2C_A004447 748 select SYS_FSL_ERRATUM_SRIO_A004034 749 select SYS_FSL_ERRATUM_USB14 750 select SYS_FSL_HAS_DDR3 751 select SYS_FSL_HAS_SEC 752 select SYS_FSL_QORIQ_CHASSIS1 753 select SYS_FSL_SEC_BE 754 select SYS_FSL_SEC_COMPAT_4 755 select SYS_PPC64 756 757config ARCH_P5040 758 bool 759 select E500MC 760 select FSL_LAW 761 select SYS_FSL_DDR_VER_44 762 select SYS_FSL_ERRATUM_A004510 763 select SYS_FSL_ERRATUM_A004699 764 select SYS_FSL_ERRATUM_A005812 765 select SYS_FSL_ERRATUM_A006261 766 select SYS_FSL_ERRATUM_DDR_A003 767 select SYS_FSL_ERRATUM_DDR_A003474 768 select SYS_FSL_ERRATUM_ESDHC111 769 select SYS_FSL_ERRATUM_USB14 770 select SYS_FSL_HAS_DDR3 771 select SYS_FSL_HAS_SEC 772 select SYS_FSL_QORIQ_CHASSIS1 773 select SYS_FSL_SEC_BE 774 select SYS_FSL_SEC_COMPAT_4 775 select SYS_PPC64 776 777config ARCH_QEMU_E500 778 bool 779 780config ARCH_T1023 781 bool 782 select E500MC 783 select FSL_LAW 784 select SYS_FSL_DDR_VER_50 785 select SYS_FSL_ERRATUM_A008378 786 select SYS_FSL_ERRATUM_A009663 787 select SYS_FSL_ERRATUM_A009942 788 select SYS_FSL_ERRATUM_ESDHC111 789 select SYS_FSL_HAS_DDR3 790 select SYS_FSL_HAS_DDR4 791 select SYS_FSL_HAS_SEC 792 select SYS_FSL_QORIQ_CHASSIS2 793 select SYS_FSL_SEC_BE 794 select SYS_FSL_SEC_COMPAT_5 795 796config ARCH_T1024 797 bool 798 select E500MC 799 select FSL_LAW 800 select SYS_FSL_DDR_VER_50 801 select SYS_FSL_ERRATUM_A008378 802 select SYS_FSL_ERRATUM_A009663 803 select SYS_FSL_ERRATUM_A009942 804 select SYS_FSL_ERRATUM_ESDHC111 805 select SYS_FSL_HAS_DDR3 806 select SYS_FSL_HAS_DDR4 807 select SYS_FSL_HAS_SEC 808 select SYS_FSL_QORIQ_CHASSIS2 809 select SYS_FSL_SEC_BE 810 select SYS_FSL_SEC_COMPAT_5 811 812config ARCH_T1040 813 bool 814 select E500MC 815 select FSL_LAW 816 select SYS_FSL_DDR_VER_50 817 select SYS_FSL_ERRATUM_A008044 818 select SYS_FSL_ERRATUM_A008378 819 select SYS_FSL_ERRATUM_A009663 820 select SYS_FSL_ERRATUM_A009942 821 select SYS_FSL_ERRATUM_ESDHC111 822 select SYS_FSL_HAS_DDR3 823 select SYS_FSL_HAS_DDR4 824 select SYS_FSL_HAS_SEC 825 select SYS_FSL_QORIQ_CHASSIS2 826 select SYS_FSL_SEC_BE 827 select SYS_FSL_SEC_COMPAT_5 828 829config ARCH_T1042 830 bool 831 select E500MC 832 select FSL_LAW 833 select SYS_FSL_DDR_VER_50 834 select SYS_FSL_ERRATUM_A008044 835 select SYS_FSL_ERRATUM_A008378 836 select SYS_FSL_ERRATUM_A009663 837 select SYS_FSL_ERRATUM_A009942 838 select SYS_FSL_ERRATUM_ESDHC111 839 select SYS_FSL_HAS_DDR3 840 select SYS_FSL_HAS_DDR4 841 select SYS_FSL_HAS_SEC 842 select SYS_FSL_QORIQ_CHASSIS2 843 select SYS_FSL_SEC_BE 844 select SYS_FSL_SEC_COMPAT_5 845 846config ARCH_T2080 847 bool 848 select E500MC 849 select E6500 850 select FSL_LAW 851 select SYS_FSL_DDR_VER_47 852 select SYS_FSL_ERRATUM_A006379 853 select SYS_FSL_ERRATUM_A006593 854 select SYS_FSL_ERRATUM_A007186 855 select SYS_FSL_ERRATUM_A007212 856 select SYS_FSL_ERRATUM_A009942 857 select SYS_FSL_ERRATUM_ESDHC111 858 select SYS_FSL_HAS_DDR3 859 select SYS_FSL_HAS_SEC 860 select SYS_FSL_QORIQ_CHASSIS2 861 select SYS_FSL_SEC_BE 862 select SYS_FSL_SEC_COMPAT_4 863 select SYS_PPC64 864 865config ARCH_T2081 866 bool 867 select E500MC 868 select E6500 869 select FSL_LAW 870 select SYS_FSL_DDR_VER_47 871 select SYS_FSL_ERRATUM_A006379 872 select SYS_FSL_ERRATUM_A006593 873 select SYS_FSL_ERRATUM_A007186 874 select SYS_FSL_ERRATUM_A007212 875 select SYS_FSL_ERRATUM_A009942 876 select SYS_FSL_ERRATUM_ESDHC111 877 select SYS_FSL_HAS_DDR3 878 select SYS_FSL_HAS_SEC 879 select SYS_FSL_QORIQ_CHASSIS2 880 select SYS_FSL_SEC_BE 881 select SYS_FSL_SEC_COMPAT_4 882 select SYS_PPC64 883 884config ARCH_T4160 885 bool 886 select E500MC 887 select E6500 888 select FSL_LAW 889 select SYS_FSL_DDR_VER_47 890 select SYS_FSL_ERRATUM_A004468 891 select SYS_FSL_ERRATUM_A005871 892 select SYS_FSL_ERRATUM_A006379 893 select SYS_FSL_ERRATUM_A006593 894 select SYS_FSL_ERRATUM_A007186 895 select SYS_FSL_ERRATUM_A007798 896 select SYS_FSL_ERRATUM_A009942 897 select SYS_FSL_HAS_DDR3 898 select SYS_FSL_HAS_SEC 899 select SYS_FSL_QORIQ_CHASSIS2 900 select SYS_FSL_SEC_BE 901 select SYS_FSL_SEC_COMPAT_4 902 select SYS_PPC64 903 904config ARCH_T4240 905 bool 906 select E500MC 907 select E6500 908 select FSL_LAW 909 select SYS_FSL_DDR_VER_47 910 select SYS_FSL_ERRATUM_A004468 911 select SYS_FSL_ERRATUM_A005871 912 select SYS_FSL_ERRATUM_A006261 913 select SYS_FSL_ERRATUM_A006379 914 select SYS_FSL_ERRATUM_A006593 915 select SYS_FSL_ERRATUM_A007186 916 select SYS_FSL_ERRATUM_A007798 917 select SYS_FSL_ERRATUM_A009942 918 select SYS_FSL_HAS_DDR3 919 select SYS_FSL_HAS_SEC 920 select SYS_FSL_QORIQ_CHASSIS2 921 select SYS_FSL_SEC_BE 922 select SYS_FSL_SEC_COMPAT_4 923 select SYS_PPC64 924 925config BOOKE 926 bool 927 default y 928 929config E500 930 bool 931 default y 932 help 933 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 934 935config E500MC 936 bool 937 help 938 Enble PowerPC E500MC core 939 940config E6500 941 bool 942 help 943 Enable PowerPC E6500 core 944 945config FSL_LAW 946 bool 947 help 948 Use Freescale common code for Local Access Window 949 950config SECURE_BOOT 951 bool "Secure Boot" 952 help 953 Enable Freescale Secure Boot feature. Normally selected 954 by defconfig. If unsure, do not change. 955 956config MAX_CPUS 957 int "Maximum number of CPUs permitted for MPC85xx" 958 default 12 if ARCH_T4240 959 default 8 if ARCH_P4080 || \ 960 ARCH_T4160 961 default 4 if ARCH_B4860 || \ 962 ARCH_P2041 || \ 963 ARCH_P3041 || \ 964 ARCH_P5040 || \ 965 ARCH_T1040 || \ 966 ARCH_T1042 || \ 967 ARCH_T2080 || \ 968 ARCH_T2081 969 default 2 if ARCH_B4420 || \ 970 ARCH_BSC9132 || \ 971 ARCH_MPC8572 || \ 972 ARCH_P1020 || \ 973 ARCH_P1021 || \ 974 ARCH_P1022 || \ 975 ARCH_P1023 || \ 976 ARCH_P1024 || \ 977 ARCH_P1025 || \ 978 ARCH_P2020 || \ 979 ARCH_P5020 || \ 980 ARCH_T1023 || \ 981 ARCH_T1024 982 default 1 983 help 984 Set this number to the maximum number of possible CPUs in the SoC. 985 SoCs may have multiple clusters with each cluster may have multiple 986 ports. If some ports are reserved but higher ports are used for 987 cores, count the reserved ports. This will allocate enough memory 988 in spin table to properly handle all cores. 989 990config SYS_CCSRBAR_DEFAULT 991 hex "Default CCSRBAR address" 992 default 0xff700000 if ARCH_BSC9131 || \ 993 ARCH_BSC9132 || \ 994 ARCH_C29X || \ 995 ARCH_MPC8536 || \ 996 ARCH_MPC8540 || \ 997 ARCH_MPC8541 || \ 998 ARCH_MPC8544 || \ 999 ARCH_MPC8548 || \ 1000 ARCH_MPC8555 || \ 1001 ARCH_MPC8560 || \ 1002 ARCH_MPC8568 || \ 1003 ARCH_MPC8569 || \ 1004 ARCH_MPC8572 || \ 1005 ARCH_P1010 || \ 1006 ARCH_P1011 || \ 1007 ARCH_P1020 || \ 1008 ARCH_P1021 || \ 1009 ARCH_P1022 || \ 1010 ARCH_P1024 || \ 1011 ARCH_P1025 || \ 1012 ARCH_P2020 1013 default 0xff600000 if ARCH_P1023 1014 default 0xfe000000 if ARCH_B4420 || \ 1015 ARCH_B4860 || \ 1016 ARCH_P2041 || \ 1017 ARCH_P3041 || \ 1018 ARCH_P4080 || \ 1019 ARCH_P5020 || \ 1020 ARCH_P5040 || \ 1021 ARCH_T1023 || \ 1022 ARCH_T1024 || \ 1023 ARCH_T1040 || \ 1024 ARCH_T1042 || \ 1025 ARCH_T2080 || \ 1026 ARCH_T2081 || \ 1027 ARCH_T4160 || \ 1028 ARCH_T4240 1029 default 0xe0000000 if ARCH_QEMU_E500 1030 help 1031 Default value of CCSRBAR comes from power-on-reset. It 1032 is fixed on each SoC. Some SoCs can have different value 1033 if changed by pre-boot regime. The value here must match 1034 the current value in SoC. If not sure, do not change. 1035 1036config SYS_FSL_ERRATUM_A004468 1037 bool 1038 1039config SYS_FSL_ERRATUM_A004477 1040 bool 1041 1042config SYS_FSL_ERRATUM_A004508 1043 bool 1044 1045config SYS_FSL_ERRATUM_A004580 1046 bool 1047 1048config SYS_FSL_ERRATUM_A004699 1049 bool 1050 1051config SYS_FSL_ERRATUM_A004849 1052 bool 1053 1054config SYS_FSL_ERRATUM_A004510 1055 bool 1056 1057config SYS_FSL_ERRATUM_A004510_SVR_REV 1058 hex 1059 depends on SYS_FSL_ERRATUM_A004510 1060 default 0x20 if ARCH_P4080 1061 default 0x10 1062 1063config SYS_FSL_ERRATUM_A004510_SVR_REV2 1064 hex 1065 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1066 default 0x11 1067 1068config SYS_FSL_ERRATUM_A005125 1069 bool 1070 1071config SYS_FSL_ERRATUM_A005434 1072 bool 1073 1074config SYS_FSL_ERRATUM_A005812 1075 bool 1076 1077config SYS_FSL_ERRATUM_A005871 1078 bool 1079 1080config SYS_FSL_ERRATUM_A006261 1081 bool 1082 1083config SYS_FSL_ERRATUM_A006379 1084 bool 1085 1086config SYS_FSL_ERRATUM_A006384 1087 bool 1088 1089config SYS_FSL_ERRATUM_A006475 1090 bool 1091 1092config SYS_FSL_ERRATUM_A006593 1093 bool 1094 1095config SYS_FSL_ERRATUM_A007075 1096 bool 1097 1098config SYS_FSL_ERRATUM_A007186 1099 bool 1100 1101config SYS_FSL_ERRATUM_A007212 1102 bool 1103 1104config SYS_FSL_ERRATUM_A007798 1105 bool 1106 1107config SYS_FSL_ERRATUM_A008044 1108 bool 1109 1110config SYS_FSL_ERRATUM_CPC_A002 1111 bool 1112 1113config SYS_FSL_ERRATUM_CPC_A003 1114 bool 1115 1116config SYS_FSL_ERRATUM_CPU_A003999 1117 bool 1118 1119config SYS_FSL_ERRATUM_ELBC_A001 1120 bool 1121 1122config SYS_FSL_ERRATUM_I2C_A004447 1123 bool 1124 1125config SYS_FSL_A004447_SVR_REV 1126 hex 1127 depends on SYS_FSL_ERRATUM_I2C_A004447 1128 default 0x00 if ARCH_MPC8548 1129 default 0x10 if ARCH_P1010 1130 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1131 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1132 1133config SYS_FSL_ERRATUM_IFC_A002769 1134 bool 1135 1136config SYS_FSL_ERRATUM_IFC_A003399 1137 bool 1138 1139config SYS_FSL_ERRATUM_NMG_CPU_A011 1140 bool 1141 1142config SYS_FSL_ERRATUM_NMG_ETSEC129 1143 bool 1144 1145config SYS_FSL_ERRATUM_NMG_LBC103 1146 bool 1147 1148config SYS_FSL_ERRATUM_P1010_A003549 1149 bool 1150 1151config SYS_FSL_ERRATUM_SATA_A001 1152 bool 1153 1154config SYS_FSL_ERRATUM_SEC_A003571 1155 bool 1156 1157config SYS_FSL_ERRATUM_SRIO_A004034 1158 bool 1159 1160config SYS_FSL_ERRATUM_USB14 1161 bool 1162 1163config SYS_P4080_ERRATUM_CPU22 1164 bool 1165 1166config SYS_P4080_ERRATUM_PCIE_A003 1167 bool 1168 1169config SYS_P4080_ERRATUM_SERDES8 1170 bool 1171 1172config SYS_P4080_ERRATUM_SERDES9 1173 bool 1174 1175config SYS_P4080_ERRATUM_SERDES_A001 1176 bool 1177 1178config SYS_P4080_ERRATUM_SERDES_A005 1179 bool 1180 1181config SYS_FSL_QORIQ_CHASSIS1 1182 bool 1183 1184config SYS_FSL_QORIQ_CHASSIS2 1185 bool 1186 1187config SYS_FSL_NUM_LAWS 1188 int "Number of local access windows" 1189 depends on FSL_LAW 1190 default 32 if ARCH_B4420 || \ 1191 ARCH_B4860 || \ 1192 ARCH_P2041 || \ 1193 ARCH_P3041 || \ 1194 ARCH_P4080 || \ 1195 ARCH_P5020 || \ 1196 ARCH_P5040 || \ 1197 ARCH_T2080 || \ 1198 ARCH_T2081 || \ 1199 ARCH_T4160 || \ 1200 ARCH_T4240 1201 default 16 if ARCH_T1023 || \ 1202 ARCH_T1024 || \ 1203 ARCH_T1040 || \ 1204 ARCH_T1042 1205 default 12 if ARCH_BSC9131 || \ 1206 ARCH_BSC9132 || \ 1207 ARCH_C29X || \ 1208 ARCH_MPC8536 || \ 1209 ARCH_MPC8572 || \ 1210 ARCH_P1010 || \ 1211 ARCH_P1011 || \ 1212 ARCH_P1020 || \ 1213 ARCH_P1021 || \ 1214 ARCH_P1022 || \ 1215 ARCH_P1023 || \ 1216 ARCH_P1024 || \ 1217 ARCH_P1025 || \ 1218 ARCH_P2020 1219 default 10 if ARCH_MPC8544 || \ 1220 ARCH_MPC8548 || \ 1221 ARCH_MPC8568 || \ 1222 ARCH_MPC8569 1223 default 8 if ARCH_MPC8540 || \ 1224 ARCH_MPC8541 || \ 1225 ARCH_MPC8555 || \ 1226 ARCH_MPC8560 1227 help 1228 Number of local access windows. This is fixed per SoC. 1229 If not sure, do not change. 1230 1231config SYS_FSL_THREADS_PER_CORE 1232 int 1233 default 2 if E6500 1234 default 1 1235 1236config SYS_NUM_TLBCAMS 1237 int "Number of TLB CAM entries" 1238 default 64 if E500MC 1239 default 16 1240 help 1241 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1242 16 for other E500 SoCs. 1243 1244config SYS_PPC64 1245 bool 1246 1247config SYS_PPC_E500_USE_DEBUG_TLB 1248 bool 1249 1250config SYS_PPC_E500_DEBUG_TLB 1251 int "Temporary TLB entry for external debugger" 1252 depends on SYS_PPC_E500_USE_DEBUG_TLB 1253 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1254 default 1 if ARCH_MPC8536 1255 default 2 if ARCH_MPC8572 || \ 1256 ARCH_P1011 || \ 1257 ARCH_P1020 || \ 1258 ARCH_P1021 || \ 1259 ARCH_P1022 || \ 1260 ARCH_P1024 || \ 1261 ARCH_P1025 || \ 1262 ARCH_P2020 1263 default 3 if ARCH_P1010 || \ 1264 ARCH_BSC9132 || \ 1265 ARCH_C29X 1266 help 1267 Select a temporary TLB entry to be used during boot to work 1268 around limitations in e500v1 and e500v2 external debugger 1269 support. This reduces the portions of the boot code where 1270 breakpoints and single stepping do not work. The value of this 1271 symbol should be set to the TLB1 entry to be used for this 1272 purpose. If unsure, do not change. 1273 1274source "board/freescale/b4860qds/Kconfig" 1275source "board/freescale/bsc9131rdb/Kconfig" 1276source "board/freescale/bsc9132qds/Kconfig" 1277source "board/freescale/c29xpcie/Kconfig" 1278source "board/freescale/corenet_ds/Kconfig" 1279source "board/freescale/mpc8536ds/Kconfig" 1280source "board/freescale/mpc8540ads/Kconfig" 1281source "board/freescale/mpc8541cds/Kconfig" 1282source "board/freescale/mpc8544ds/Kconfig" 1283source "board/freescale/mpc8548cds/Kconfig" 1284source "board/freescale/mpc8555cds/Kconfig" 1285source "board/freescale/mpc8560ads/Kconfig" 1286source "board/freescale/mpc8568mds/Kconfig" 1287source "board/freescale/mpc8569mds/Kconfig" 1288source "board/freescale/mpc8572ds/Kconfig" 1289source "board/freescale/p1010rdb/Kconfig" 1290source "board/freescale/p1022ds/Kconfig" 1291source "board/freescale/p1023rdb/Kconfig" 1292source "board/freescale/p1_p2_rdb_pc/Kconfig" 1293source "board/freescale/p1_twr/Kconfig" 1294source "board/freescale/p2041rdb/Kconfig" 1295source "board/freescale/qemu-ppce500/Kconfig" 1296source "board/freescale/t102xqds/Kconfig" 1297source "board/freescale/t102xrdb/Kconfig" 1298source "board/freescale/t1040qds/Kconfig" 1299source "board/freescale/t104xrdb/Kconfig" 1300source "board/freescale/t208xqds/Kconfig" 1301source "board/freescale/t208xrdb/Kconfig" 1302source "board/freescale/t4qds/Kconfig" 1303source "board/freescale/t4rdb/Kconfig" 1304source "board/gdsys/p1022/Kconfig" 1305source "board/keymile/kmp204x/Kconfig" 1306source "board/sbc8548/Kconfig" 1307source "board/socrates/Kconfig" 1308source "board/varisys/cyrus/Kconfig" 1309source "board/xes/xpedite520x/Kconfig" 1310source "board/xes/xpedite537x/Kconfig" 1311source "board/xes/xpedite550x/Kconfig" 1312source "board/Arcturus/ucp1020/Kconfig" 1313 1314endmenu 1315