1/* 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 28 */ 29 30#include <config.h> 31#include <mpc83xx.h> 32#include <timestamp.h> 33#include <version.h> 34 35#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 36#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 37 38#include <ppc_asm.tmpl> 39#include <ppc_defs.h> 40 41#include <asm/cache.h> 42#include <asm/mmu.h> 43 44#ifndef CONFIG_IDENT_STRING 45#define CONFIG_IDENT_STRING "MPC83XX" 46#endif 47 48/* We don't want the MMU yet. 49 */ 50#undef MSR_KERNEL 51 52/* 53 * Floating Point enable, Machine Check and Recoverable Interr. 54 */ 55#ifdef DEBUG 56#define MSR_KERNEL (MSR_FP|MSR_RI) 57#else 58#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 59#endif 60 61#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT) 62#define CONFIG_SYS_FLASHBOOT 63#endif 64 65/* 66 * Set up GOT: Global Offset Table 67 * 68 * Use r12 to access the GOT 69 */ 70 START_GOT 71 GOT_ENTRY(_GOT2_TABLE_) 72 GOT_ENTRY(__bss_start) 73 GOT_ENTRY(_end) 74 75#ifndef CONFIG_NAND_SPL 76 GOT_ENTRY(_FIXUP_TABLE_) 77 GOT_ENTRY(_start) 78 GOT_ENTRY(_start_of_vectors) 79 GOT_ENTRY(_end_of_vectors) 80 GOT_ENTRY(transfer_to_handler) 81#endif 82 END_GOT 83 84/* 85 * The Hard Reset Configuration Word (HRCW) table is in the first 64 86 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 87 * times so the processor can fetch it out of flash whether the flash 88 * is 8, 16, 32, or 64 bits wide (hardware trickery). 89 */ 90 .text 91#define _HRCW_TABLE_ENTRY(w) \ 92 .fill 8,1,(((w)>>24)&0xff); \ 93 .fill 8,1,(((w)>>16)&0xff); \ 94 .fill 8,1,(((w)>> 8)&0xff); \ 95 .fill 8,1,(((w) )&0xff) 96 97 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 98 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 99 100/* 101 * Magic number and version string - put it after the HRCW since it 102 * cannot be first in flash like it is in many other processors. 103 */ 104 .long 0x27051956 /* U-Boot Magic Number */ 105 106 .globl version_string 107version_string: 108 .ascii U_BOOT_VERSION 109 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" 110 .ascii " ", CONFIG_IDENT_STRING, "\0" 111 112 .align 2 113 114 .globl enable_addr_trans 115enable_addr_trans: 116 /* enable address translation */ 117 mfmsr r5 118 ori r5, r5, (MSR_IR | MSR_DR) 119 mtmsr r5 120 isync 121 blr 122 123 .globl disable_addr_trans 124disable_addr_trans: 125 /* disable address translation */ 126 mflr r4 127 mfmsr r3 128 andi. r0, r3, (MSR_IR | MSR_DR) 129 beqlr 130 andc r3, r3, r0 131 mtspr SRR0, r4 132 mtspr SRR1, r3 133 rfi 134 135 .globl get_pvr 136get_pvr: 137 mfspr r3, PVR 138 blr 139 140 .globl ppcDWstore 141ppcDWstore: 142 lfd 1, 0(r4) 143 stfd 1, 0(r3) 144 blr 145 146 .globl ppcDWload 147ppcDWload: 148 lfd 1, 0(r3) 149 stfd 1, 0(r4) 150 blr 151 152#ifndef CONFIG_DEFAULT_IMMR 153#error CONFIG_DEFAULT_IMMR must be defined 154#endif /* CONFIG_SYS_DEFAULT_IMMR */ 155#ifndef CONFIG_SYS_IMMR 156#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 157#endif /* CONFIG_SYS_IMMR */ 158 159/* 160 * After configuration, a system reset exception is executed using the 161 * vector at offset 0x100 relative to the base set by MSR[IP]. If 162 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 163 * base address is 0xfff00000. In the case of a Power On Reset or Hard 164 * Reset, the value of MSR[IP] is determined by the CIP field in the 165 * HRCW. 166 * 167 * Other bits in the HRCW set up the Base Address and Port Size in BR0. 168 * This determines the location of the boot ROM (flash or EPROM) in the 169 * processor's address space at boot time. As long as the HRCW is set up 170 * so that we eventually end up executing the code below when the 171 * processor executes the reset exception, the actual values used should 172 * not matter. 173 * 174 * Once we have got here, the address mask in OR0 is cleared so that the 175 * bottom 32K of the boot ROM is effectively repeated all throughout the 176 * processor's address space, after which we can jump to the absolute 177 * address at which the boot ROM was linked at compile time, and proceed 178 * to initialise the memory controller without worrying if the rug will 179 * be pulled out from under us, so to speak (it will be fine as long as 180 * we configure BR0 with the same boot ROM link address). 181 */ 182 . = EXC_OFF_SYS_RESET 183 184 .globl _start 185_start: /* time t 0 */ 186 lis r4, CONFIG_DEFAULT_IMMR@h 187 nop 188 189 mfmsr r5 /* save msr contents */ 190 191 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 192 bl 1f 1931: mflr r7 194 195 lis r3, CONFIG_SYS_IMMR@h 196 ori r3, r3, CONFIG_SYS_IMMR@l 197 198 lwz r6, IMMRBAR(r4) 199 isync 200 201 stw r3, IMMRBAR(r4) 202 lwz r6, 0(r7) /* Arbitrary external load */ 203 isync 204 205 lwz r6, IMMRBAR(r3) 206 isync 207 208 /* Initialise the E300 processor core */ 209 /*------------------------------------------*/ 210 211#ifdef CONFIG_NAND_SPL 212 /* The FCM begins execution after only the first page 213 * is loaded. Wait for the rest before branching 214 * to another flash page. 215 */ 2161: lwz r6, 0x50b0(r3) 217 andi. r6, r6, 1 218 beq 1b 219#endif 220 221 bl init_e300_core 222 223#ifdef CONFIG_SYS_FLASHBOOT 224 225 /* Inflate flash location so it appears everywhere, calculate */ 226 /* the absolute address in final location of the FLASH, jump */ 227 /* there and deflate the flash size back to minimal size */ 228 /*------------------------------------------------------------*/ 229 bl map_flash_by_law1 230 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 231 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 232 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 233 mtlr r5 234 blr 235in_flash: 236#if 1 /* Remapping flash with LAW0. */ 237 bl remap_flash_by_law0 238#endif 239#endif /* CONFIG_SYS_FLASHBOOT */ 240 241 /* setup the bats */ 242 bl setup_bats 243 sync 244 245 /* 246 * Cache must be enabled here for stack-in-cache trick. 247 * This means we need to enable the BATS. 248 * This means: 249 * 1) for the EVB, original gt regs need to be mapped 250 * 2) need to have an IBAT for the 0xf region, 251 * we are running there! 252 * Cache should be turned on after BATs, since by default 253 * everything is write-through. 254 * The init-mem BAT can be reused after reloc. The old 255 * gt-regs BAT can be reused after board_init_f calls 256 * board_early_init_f (EVB only). 257 */ 258 /* enable address translation */ 259 bl enable_addr_trans 260 sync 261 262 /* enable the data cache */ 263 bl dcache_enable 264 sync 265#ifdef CONFIG_SYS_INIT_RAM_LOCK 266 bl lock_ram_in_cache 267 sync 268#endif 269 270 /* set up the stack pointer in our newly created 271 * cache-ram (r1) */ 272 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 273 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 274 275 li r0, 0 /* Make room for stack frame header and */ 276 stwu r0, -4(r1) /* clear final stack frame so that */ 277 stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 278 279 280 /* let the C-code set up the rest */ 281 /* */ 282 /* Be careful to keep code relocatable & stack humble */ 283 /*------------------------------------------------------*/ 284 285 GET_GOT /* initialize GOT access */ 286 287 /* r3: IMMR */ 288 lis r3, CONFIG_SYS_IMMR@h 289 /* run low-level CPU init code (in Flash)*/ 290 bl cpu_init_f 291 292 /* run 1st part of board init code (in Flash)*/ 293 bl board_init_f 294 295 /* NOTREACHED - board_init_f() does not return */ 296 297#ifndef CONFIG_NAND_SPL 298/* 299 * Vector Table 300 */ 301 302 .globl _start_of_vectors 303_start_of_vectors: 304 305/* Machine check */ 306 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 307 308/* Data Storage exception. */ 309 STD_EXCEPTION(0x300, DataStorage, UnknownException) 310 311/* Instruction Storage exception. */ 312 STD_EXCEPTION(0x400, InstStorage, UnknownException) 313 314/* External Interrupt exception. */ 315#ifndef FIXME 316 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 317#endif 318 319/* Alignment exception. */ 320 . = 0x600 321Alignment: 322 EXCEPTION_PROLOG(SRR0, SRR1) 323 mfspr r4,DAR 324 stw r4,_DAR(r21) 325 mfspr r5,DSISR 326 stw r5,_DSISR(r21) 327 addi r3,r1,STACK_FRAME_OVERHEAD 328 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 329 330/* Program check exception */ 331 . = 0x700 332ProgramCheck: 333 EXCEPTION_PROLOG(SRR0, SRR1) 334 addi r3,r1,STACK_FRAME_OVERHEAD 335 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 336 MSR_KERNEL, COPY_EE) 337 338 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 339 340 /* I guess we could implement decrementer, and may have 341 * to someday for timekeeping. 342 */ 343 STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 344 345 STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 346 STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 347 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 348 STD_EXCEPTION(0xd00, SingleStep, UnknownException) 349 350 STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 351 STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 352 353 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 354 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 355 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 356#ifdef DEBUG 357 . = 0x1300 358 /* 359 * This exception occurs when the program counter matches the 360 * Instruction Address Breakpoint Register (IABR). 361 * 362 * I want the cpu to halt if this occurs so I can hunt around 363 * with the debugger and look at things. 364 * 365 * When DEBUG is defined, both machine check enable (in the MSR) 366 * and checkstop reset enable (in the reset mode register) are 367 * turned off and so a checkstop condition will result in the cpu 368 * halting. 369 * 370 * I force the cpu into a checkstop condition by putting an illegal 371 * instruction here (at least this is the theory). 372 * 373 * well - that didnt work, so just do an infinite loop! 374 */ 3751: b 1b 376#else 377 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 378#endif 379 STD_EXCEPTION(0x1400, SMI, UnknownException) 380 381 STD_EXCEPTION(0x1500, Trap_15, UnknownException) 382 STD_EXCEPTION(0x1600, Trap_16, UnknownException) 383 STD_EXCEPTION(0x1700, Trap_17, UnknownException) 384 STD_EXCEPTION(0x1800, Trap_18, UnknownException) 385 STD_EXCEPTION(0x1900, Trap_19, UnknownException) 386 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 387 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 388 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 389 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 390 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 391 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 392 STD_EXCEPTION(0x2000, Trap_20, UnknownException) 393 STD_EXCEPTION(0x2100, Trap_21, UnknownException) 394 STD_EXCEPTION(0x2200, Trap_22, UnknownException) 395 STD_EXCEPTION(0x2300, Trap_23, UnknownException) 396 STD_EXCEPTION(0x2400, Trap_24, UnknownException) 397 STD_EXCEPTION(0x2500, Trap_25, UnknownException) 398 STD_EXCEPTION(0x2600, Trap_26, UnknownException) 399 STD_EXCEPTION(0x2700, Trap_27, UnknownException) 400 STD_EXCEPTION(0x2800, Trap_28, UnknownException) 401 STD_EXCEPTION(0x2900, Trap_29, UnknownException) 402 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 403 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 404 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 405 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 406 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 407 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 408 409 410 .globl _end_of_vectors 411_end_of_vectors: 412 413 . = 0x3000 414 415/* 416 * This code finishes saving the registers to the exception frame 417 * and jumps to the appropriate handler for the exception. 418 * Register r21 is pointer into trap frame, r1 has new stack pointer. 419 */ 420 .globl transfer_to_handler 421transfer_to_handler: 422 stw r22,_NIP(r21) 423 lis r22,MSR_POW@h 424 andc r23,r23,r22 425 stw r23,_MSR(r21) 426 SAVE_GPR(7, r21) 427 SAVE_4GPRS(8, r21) 428 SAVE_8GPRS(12, r21) 429 SAVE_8GPRS(24, r21) 430 mflr r23 431 andi. r24,r23,0x3f00 /* get vector offset */ 432 stw r24,TRAP(r21) 433 li r22,0 434 stw r22,RESULT(r21) 435 lwz r24,0(r23) /* virtual address of handler */ 436 lwz r23,4(r23) /* where to go when done */ 437 mtspr SRR0,r24 438 mtspr SRR1,r20 439 mtlr r23 440 SYNC 441 rfi /* jump to handler, enable MMU */ 442 443int_return: 444 mfmsr r28 /* Disable interrupts */ 445 li r4,0 446 ori r4,r4,MSR_EE 447 andc r28,r28,r4 448 SYNC /* Some chip revs need this... */ 449 mtmsr r28 450 SYNC 451 lwz r2,_CTR(r1) 452 lwz r0,_LINK(r1) 453 mtctr r2 454 mtlr r0 455 lwz r2,_XER(r1) 456 lwz r0,_CCR(r1) 457 mtspr XER,r2 458 mtcrf 0xFF,r0 459 REST_10GPRS(3, r1) 460 REST_10GPRS(13, r1) 461 REST_8GPRS(23, r1) 462 REST_GPR(31, r1) 463 lwz r2,_NIP(r1) /* Restore environment */ 464 lwz r0,_MSR(r1) 465 mtspr SRR0,r2 466 mtspr SRR1,r0 467 lwz r0,GPR0(r1) 468 lwz r2,GPR2(r1) 469 lwz r1,GPR1(r1) 470 SYNC 471 rfi 472#endif /* !CONFIG_NAND_SPL */ 473 474/* 475 * This code initialises the E300 processor core 476 * (conforms to PowerPC 603e spec) 477 * Note: expects original MSR contents to be in r5. 478 */ 479 .globl init_e300_core 480init_e300_core: /* time t 10 */ 481 /* Initialize machine status; enable machine check interrupt */ 482 /*-----------------------------------------------------------*/ 483 484 li r3, MSR_KERNEL /* Set ME and RI flags */ 485 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 486#ifdef DEBUG 487 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 488#endif 489 SYNC /* Some chip revs need this... */ 490 mtmsr r3 491 SYNC 492 mtspr SRR1, r3 /* Make SRR1 match MSR */ 493 494 495 lis r3, CONFIG_SYS_IMMR@h 496#if defined(CONFIG_WATCHDOG) 497 /* Initialise the Watchdog values and reset it (if req) */ 498 /*------------------------------------------------------*/ 499 lis r4, CONFIG_SYS_WATCHDOG_VALUE 500 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 501 stw r4, SWCRR(r3) 502 503 /* and reset it */ 504 505 li r4, 0x556C 506 sth r4, SWSRR@l(r3) 507 li r4, -0x55C7 508 sth r4, SWSRR@l(r3) 509#else 510 /* Disable Watchdog */ 511 /*-------------------*/ 512 lwz r4, SWCRR(r3) 513 /* Check to see if its enabled for disabling 514 once disabled by SW you can't re-enable */ 515 andi. r4, r4, 0x4 516 beq 1f 517 xor r4, r4, r4 518 stw r4, SWCRR(r3) 5191: 520#endif /* CONFIG_WATCHDOG */ 521 522#if defined(CONFIG_MASK_AER_AO) 523 /* Write the Arbiter Event Enable to mask Address Only traps. */ 524 /* This prevents the dcbz instruction from being trapped when */ 525 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 526 /* COHERENCY bit is set in the WIMG bits, which is often */ 527 /* needed for PCI operation. */ 528 lwz r4, 0x0808(r3) 529 rlwinm r0, r4, 0, ~AER_AO 530 stw r0, 0x0808(r3) 531#endif /* CONFIG_MASK_AER_AO */ 532 533 /* Initialize the Hardware Implementation-dependent Registers */ 534 /* HID0 also contains cache control */ 535 /* - force invalidation of data and instruction caches */ 536 /*------------------------------------------------------*/ 537 538 lis r3, CONFIG_SYS_HID0_INIT@h 539 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 540 SYNC 541 mtspr HID0, r3 542 543 lis r3, CONFIG_SYS_HID0_FINAL@h 544 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 545 SYNC 546 mtspr HID0, r3 547 548 lis r3, CONFIG_SYS_HID2@h 549 ori r3, r3, CONFIG_SYS_HID2@l 550 SYNC 551 mtspr HID2, r3 552 553 /* Done! */ 554 /*------------------------------*/ 555 blr 556 557 /* setup_bats - set them up to some initial state */ 558 .globl setup_bats 559setup_bats: 560 addis r0, r0, 0x0000 561 562 /* IBAT 0 */ 563 addis r4, r0, CONFIG_SYS_IBAT0L@h 564 ori r4, r4, CONFIG_SYS_IBAT0L@l 565 addis r3, r0, CONFIG_SYS_IBAT0U@h 566 ori r3, r3, CONFIG_SYS_IBAT0U@l 567 mtspr IBAT0L, r4 568 mtspr IBAT0U, r3 569 570 /* DBAT 0 */ 571 addis r4, r0, CONFIG_SYS_DBAT0L@h 572 ori r4, r4, CONFIG_SYS_DBAT0L@l 573 addis r3, r0, CONFIG_SYS_DBAT0U@h 574 ori r3, r3, CONFIG_SYS_DBAT0U@l 575 mtspr DBAT0L, r4 576 mtspr DBAT0U, r3 577 578 /* IBAT 1 */ 579 addis r4, r0, CONFIG_SYS_IBAT1L@h 580 ori r4, r4, CONFIG_SYS_IBAT1L@l 581 addis r3, r0, CONFIG_SYS_IBAT1U@h 582 ori r3, r3, CONFIG_SYS_IBAT1U@l 583 mtspr IBAT1L, r4 584 mtspr IBAT1U, r3 585 586 /* DBAT 1 */ 587 addis r4, r0, CONFIG_SYS_DBAT1L@h 588 ori r4, r4, CONFIG_SYS_DBAT1L@l 589 addis r3, r0, CONFIG_SYS_DBAT1U@h 590 ori r3, r3, CONFIG_SYS_DBAT1U@l 591 mtspr DBAT1L, r4 592 mtspr DBAT1U, r3 593 594 /* IBAT 2 */ 595 addis r4, r0, CONFIG_SYS_IBAT2L@h 596 ori r4, r4, CONFIG_SYS_IBAT2L@l 597 addis r3, r0, CONFIG_SYS_IBAT2U@h 598 ori r3, r3, CONFIG_SYS_IBAT2U@l 599 mtspr IBAT2L, r4 600 mtspr IBAT2U, r3 601 602 /* DBAT 2 */ 603 addis r4, r0, CONFIG_SYS_DBAT2L@h 604 ori r4, r4, CONFIG_SYS_DBAT2L@l 605 addis r3, r0, CONFIG_SYS_DBAT2U@h 606 ori r3, r3, CONFIG_SYS_DBAT2U@l 607 mtspr DBAT2L, r4 608 mtspr DBAT2U, r3 609 610 /* IBAT 3 */ 611 addis r4, r0, CONFIG_SYS_IBAT3L@h 612 ori r4, r4, CONFIG_SYS_IBAT3L@l 613 addis r3, r0, CONFIG_SYS_IBAT3U@h 614 ori r3, r3, CONFIG_SYS_IBAT3U@l 615 mtspr IBAT3L, r4 616 mtspr IBAT3U, r3 617 618 /* DBAT 3 */ 619 addis r4, r0, CONFIG_SYS_DBAT3L@h 620 ori r4, r4, CONFIG_SYS_DBAT3L@l 621 addis r3, r0, CONFIG_SYS_DBAT3U@h 622 ori r3, r3, CONFIG_SYS_DBAT3U@l 623 mtspr DBAT3L, r4 624 mtspr DBAT3U, r3 625 626#ifdef CONFIG_HIGH_BATS 627 /* IBAT 4 */ 628 addis r4, r0, CONFIG_SYS_IBAT4L@h 629 ori r4, r4, CONFIG_SYS_IBAT4L@l 630 addis r3, r0, CONFIG_SYS_IBAT4U@h 631 ori r3, r3, CONFIG_SYS_IBAT4U@l 632 mtspr IBAT4L, r4 633 mtspr IBAT4U, r3 634 635 /* DBAT 4 */ 636 addis r4, r0, CONFIG_SYS_DBAT4L@h 637 ori r4, r4, CONFIG_SYS_DBAT4L@l 638 addis r3, r0, CONFIG_SYS_DBAT4U@h 639 ori r3, r3, CONFIG_SYS_DBAT4U@l 640 mtspr DBAT4L, r4 641 mtspr DBAT4U, r3 642 643 /* IBAT 5 */ 644 addis r4, r0, CONFIG_SYS_IBAT5L@h 645 ori r4, r4, CONFIG_SYS_IBAT5L@l 646 addis r3, r0, CONFIG_SYS_IBAT5U@h 647 ori r3, r3, CONFIG_SYS_IBAT5U@l 648 mtspr IBAT5L, r4 649 mtspr IBAT5U, r3 650 651 /* DBAT 5 */ 652 addis r4, r0, CONFIG_SYS_DBAT5L@h 653 ori r4, r4, CONFIG_SYS_DBAT5L@l 654 addis r3, r0, CONFIG_SYS_DBAT5U@h 655 ori r3, r3, CONFIG_SYS_DBAT5U@l 656 mtspr DBAT5L, r4 657 mtspr DBAT5U, r3 658 659 /* IBAT 6 */ 660 addis r4, r0, CONFIG_SYS_IBAT6L@h 661 ori r4, r4, CONFIG_SYS_IBAT6L@l 662 addis r3, r0, CONFIG_SYS_IBAT6U@h 663 ori r3, r3, CONFIG_SYS_IBAT6U@l 664 mtspr IBAT6L, r4 665 mtspr IBAT6U, r3 666 667 /* DBAT 6 */ 668 addis r4, r0, CONFIG_SYS_DBAT6L@h 669 ori r4, r4, CONFIG_SYS_DBAT6L@l 670 addis r3, r0, CONFIG_SYS_DBAT6U@h 671 ori r3, r3, CONFIG_SYS_DBAT6U@l 672 mtspr DBAT6L, r4 673 mtspr DBAT6U, r3 674 675 /* IBAT 7 */ 676 addis r4, r0, CONFIG_SYS_IBAT7L@h 677 ori r4, r4, CONFIG_SYS_IBAT7L@l 678 addis r3, r0, CONFIG_SYS_IBAT7U@h 679 ori r3, r3, CONFIG_SYS_IBAT7U@l 680 mtspr IBAT7L, r4 681 mtspr IBAT7U, r3 682 683 /* DBAT 7 */ 684 addis r4, r0, CONFIG_SYS_DBAT7L@h 685 ori r4, r4, CONFIG_SYS_DBAT7L@l 686 addis r3, r0, CONFIG_SYS_DBAT7U@h 687 ori r3, r3, CONFIG_SYS_DBAT7U@l 688 mtspr DBAT7L, r4 689 mtspr DBAT7U, r3 690#endif 691 692 isync 693 694 /* invalidate all tlb's 695 * 696 * From the 603e User Manual: "The 603e provides the ability to 697 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 698 * instruction invalidates the TLB entry indexed by the EA, and 699 * operates on both the instruction and data TLBs simultaneously 700 * invalidating four TLB entries (both sets in each TLB). The 701 * index corresponds to bits 15-19 of the EA. To invalidate all 702 * entries within both TLBs, 32 tlbie instructions should be 703 * issued, incrementing this field by one each time." 704 * 705 * "Note that the tlbia instruction is not implemented on the 706 * 603e." 707 * 708 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 709 * incrementing by 0x1000 each time. The code below is sort of 710 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 711 * 712 */ 713 lis r3, 0 714 lis r5, 2 715 7161: 717 tlbie r3 718 addi r3, r3, 0x1000 719 cmp 0, 0, r3, r5 720 blt 1b 721 722 blr 723 724/* Cache functions. 725 * 726 * Note: requires that all cache bits in 727 * HID0 are in the low half word. 728 */ 729#ifndef CONFIG_NAND_SPL 730 .globl icache_enable 731icache_enable: 732 mfspr r3, HID0 733 ori r3, r3, HID0_ICE 734 li r4, HID0_ICFI|HID0_ILOCK 735 andc r3, r3, r4 736 ori r4, r3, HID0_ICFI 737 isync 738 mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 739 isync 740 mtspr HID0, r3 /* clears invalidate */ 741 blr 742 743 .globl icache_disable 744icache_disable: 745 mfspr r3, HID0 746 lis r4, 0 747 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 748 andc r3, r3, r4 749 isync 750 mtspr HID0, r3 /* clears invalidate, enable and lock */ 751 blr 752 753 .globl icache_status 754icache_status: 755 mfspr r3, HID0 756 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 757 blr 758#endif /* !CONFIG_NAND_SPL */ 759 760 .globl dcache_enable 761dcache_enable: 762 mfspr r3, HID0 763 li r5, HID0_DCFI|HID0_DLOCK 764 andc r3, r3, r5 765 ori r3, r3, HID0_DCE 766 sync 767 mtspr HID0, r3 /* enable, no invalidate */ 768 blr 769 770 .globl dcache_disable 771dcache_disable: 772 mflr r4 773 bl flush_dcache /* uses r3 and r5 */ 774 mfspr r3, HID0 775 li r5, HID0_DCE|HID0_DLOCK 776 andc r3, r3, r5 777 ori r5, r3, HID0_DCFI 778 sync 779 mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 780 sync 781 mtspr HID0, r3 /* clears invalidate */ 782 mtlr r4 783 blr 784 785 .globl dcache_status 786dcache_status: 787 mfspr r3, HID0 788 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 789 blr 790 791 .globl flush_dcache 792flush_dcache: 793 lis r3, 0 794 lis r5, CONFIG_SYS_CACHELINE_SIZE 7951: cmp 0, 1, r3, r5 796 bge 2f 797 lwz r5, 0(r3) 798 lis r5, CONFIG_SYS_CACHELINE_SIZE 799 addi r3, r3, 0x4 800 b 1b 8012: blr 802 803/*-------------------------------------------------------------------*/ 804 805/* 806 * void relocate_code (addr_sp, gd, addr_moni) 807 * 808 * This "function" does not return, instead it continues in RAM 809 * after relocating the monitor code. 810 * 811 * r3 = dest 812 * r4 = src 813 * r5 = length in bytes 814 * r6 = cachelinesize 815 */ 816 .globl relocate_code 817relocate_code: 818 mr r1, r3 /* Set new stack pointer */ 819 mr r9, r4 /* Save copy of Global Data pointer */ 820 mr r10, r5 /* Save copy of Destination Address */ 821 822 GET_GOT 823 mr r3, r5 /* Destination Address */ 824 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 825 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 826 lwz r5, GOT(__bss_start) 827 sub r5, r5, r4 828 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 829 830 /* 831 * Fix GOT pointer: 832 * 833 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 834 * + Destination Address 835 * 836 * Offset: 837 */ 838 sub r15, r10, r4 839 840 /* First our own GOT */ 841 add r12, r12, r15 842 /* then the one used by the C code */ 843 add r30, r30, r15 844 845 /* 846 * Now relocate code 847 */ 848 849 cmplw cr1,r3,r4 850 addi r0,r5,3 851 srwi. r0,r0,2 852 beq cr1,4f /* In place copy is not necessary */ 853 beq 7f /* Protect against 0 count */ 854 mtctr r0 855 bge cr1,2f 856 la r8,-4(r4) 857 la r7,-4(r3) 858 859 /* copy */ 8601: lwzu r0,4(r8) 861 stwu r0,4(r7) 862 bdnz 1b 863 864 addi r0,r5,3 865 srwi. r0,r0,2 866 mtctr r0 867 la r8,-4(r4) 868 la r7,-4(r3) 869 870 /* and compare */ 87120: lwzu r20,4(r8) 872 lwzu r21,4(r7) 873 xor. r22, r20, r21 874 bne 30f 875 bdnz 20b 876 b 4f 877 878 /* compare failed */ 87930: li r3, 0 880 blr 881 8822: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 883 add r8,r4,r0 884 add r7,r3,r0 8853: lwzu r0,-4(r8) 886 stwu r0,-4(r7) 887 bdnz 3b 888 889/* 890 * Now flush the cache: note that we must start from a cache aligned 891 * address. Otherwise we might miss one cache line. 892 */ 8934: cmpwi r6,0 894 add r5,r3,r5 895 beq 7f /* Always flush prefetch queue in any case */ 896 subi r0,r6,1 897 andc r3,r3,r0 898 mr r4,r3 8995: dcbst 0,r4 900 add r4,r4,r6 901 cmplw r4,r5 902 blt 5b 903 sync /* Wait for all dcbst to complete on bus */ 904 mr r4,r3 9056: icbi 0,r4 906 add r4,r4,r6 907 cmplw r4,r5 908 blt 6b 9097: sync /* Wait for all icbi to complete on bus */ 910 isync 911 912/* 913 * We are done. Do not return, instead branch to second part of board 914 * initialization, now running from RAM. 915 */ 916 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 917 mtlr r0 918 blr 919 920in_ram: 921 922 /* 923 * Relocation Function, r12 point to got2+0x8000 924 * 925 * Adjust got2 pointers, no need to check for 0, this code 926 * already puts a few entries in the table. 927 */ 928 li r0,__got2_entries@sectoff@l 929 la r3,GOT(_GOT2_TABLE_) 930 lwz r11,GOT(_GOT2_TABLE_) 931 mtctr r0 932 sub r11,r3,r11 933 addi r3,r3,-4 9341: lwzu r0,4(r3) 935 cmpwi r0,0 936 beq- 2f 937 add r0,r0,r11 938 stw r0,0(r3) 9392: bdnz 1b 940 941#ifndef CONFIG_NAND_SPL 942 /* 943 * Now adjust the fixups and the pointers to the fixups 944 * in case we need to move ourselves again. 945 */ 946 li r0,__fixup_entries@sectoff@l 947 lwz r3,GOT(_FIXUP_TABLE_) 948 cmpwi r0,0 949 mtctr r0 950 addi r3,r3,-4 951 beq 4f 9523: lwzu r4,4(r3) 953 lwzux r0,r4,r11 954 add r0,r0,r11 955 stw r10,0(r3) 956 stw r0,0(r4) 957 bdnz 3b 9584: 959#endif 960 961clear_bss: 962 /* 963 * Now clear BSS segment 964 */ 965 lwz r3,GOT(__bss_start) 966#if defined(CONFIG_HYMOD) 967 /* 968 * For HYMOD - the environment is the very last item in flash. 969 * The real .bss stops just before environment starts, so only 970 * clear up to that point. 971 * 972 * taken from mods for FADS board 973 */ 974 lwz r4,GOT(environment) 975#else 976 lwz r4,GOT(_end) 977#endif 978 979 cmplw 0, r3, r4 980 beq 6f 981 982 li r0, 0 9835: 984 stw r0, 0(r3) 985 addi r3, r3, 4 986 cmplw 0, r3, r4 987 bne 5b 9886: 989 990 mr r3, r9 /* Global Data pointer */ 991 mr r4, r10 /* Destination Address */ 992 bl board_init_r 993 994#ifndef CONFIG_NAND_SPL 995 /* 996 * Copy exception vector code to low memory 997 * 998 * r3: dest_addr 999 * r7: source address, r8: end address, r9: target address 1000 */ 1001 .globl trap_init 1002trap_init: 1003 mflr r4 /* save link register */ 1004 GET_GOT 1005 lwz r7, GOT(_start) 1006 lwz r8, GOT(_end_of_vectors) 1007 1008 li r9, 0x100 /* reset vector always at 0x100 */ 1009 1010 cmplw 0, r7, r8 1011 bgelr /* return if r7>=r8 - just in case */ 10121: 1013 lwz r0, 0(r7) 1014 stw r0, 0(r9) 1015 addi r7, r7, 4 1016 addi r9, r9, 4 1017 cmplw 0, r7, r8 1018 bne 1b 1019 1020 /* 1021 * relocate `hdlr' and `int_return' entries 1022 */ 1023 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1024 li r8, Alignment - _start + EXC_OFF_SYS_RESET 10252: 1026 bl trap_reloc 1027 addi r7, r7, 0x100 /* next exception vector */ 1028 cmplw 0, r7, r8 1029 blt 2b 1030 1031 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1032 bl trap_reloc 1033 1034 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1035 bl trap_reloc 1036 1037 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1038 li r8, SystemCall - _start + EXC_OFF_SYS_RESET 10393: 1040 bl trap_reloc 1041 addi r7, r7, 0x100 /* next exception vector */ 1042 cmplw 0, r7, r8 1043 blt 3b 1044 1045 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1046 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 10474: 1048 bl trap_reloc 1049 addi r7, r7, 0x100 /* next exception vector */ 1050 cmplw 0, r7, r8 1051 blt 4b 1052 1053 mfmsr r3 /* now that the vectors have */ 1054 lis r7, MSR_IP@h /* relocated into low memory */ 1055 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1056 andc r3, r3, r7 /* (if it was on) */ 1057 SYNC /* Some chip revs need this... */ 1058 mtmsr r3 1059 SYNC 1060 1061 mtlr r4 /* restore link register */ 1062 blr 1063 1064#endif /* !CONFIG_NAND_SPL */ 1065 1066#ifdef CONFIG_SYS_INIT_RAM_LOCK 1067lock_ram_in_cache: 1068 /* Allocate Initial RAM in data cache. 1069 */ 1070 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1071 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1072 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ 1073 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1074 mtctr r4 10751: 1076 dcbz r0, r3 1077 addi r3, r3, 32 1078 bdnz 1b 1079 1080 /* Lock the data cache */ 1081 mfspr r0, HID0 1082 ori r0, r0, HID0_DLOCK 1083 sync 1084 mtspr HID0, r0 1085 sync 1086 blr 1087 1088#ifndef CONFIG_NAND_SPL 1089.globl unlock_ram_in_cache 1090unlock_ram_in_cache: 1091 /* invalidate the INIT_RAM section */ 1092 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1093 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1094 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ 1095 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1096 mtctr r4 10971: icbi r0, r3 1098 dcbi r0, r3 1099 addi r3, r3, 32 1100 bdnz 1b 1101 sync /* Wait for all icbi to complete on bus */ 1102 isync 1103 1104 /* Unlock the data cache and invalidate it */ 1105 mfspr r3, HID0 1106 li r5, HID0_DLOCK|HID0_DCFI 1107 andc r3, r3, r5 /* no invalidate, unlock */ 1108 ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1109 sync 1110 mtspr HID0, r5 /* invalidate, unlock */ 1111 sync 1112 mtspr HID0, r3 /* no invalidate, unlock */ 1113 blr 1114#endif /* !CONFIG_NAND_SPL */ 1115#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1116 1117#ifdef CONFIG_SYS_FLASHBOOT 1118map_flash_by_law1: 1119 /* When booting from ROM (Flash or EPROM), clear the */ 1120 /* Address Mask in OR0 so ROM appears everywhere */ 1121 /*----------------------------------------------------*/ 1122 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1123 lwz r4, OR0@l(r3) 1124 li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1125 and r4, r4, r5 1126 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1127 1128 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1129 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1130 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1131 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1132 * 0xFF800. From the hard resetting to here, the processor fetched and 1133 * executed the instructions one by one. There is not absolutely 1134 * jumping happened. Laterly, the u-boot code has to do an absolutely 1135 * jumping to tell the CPU instruction fetching component what the 1136 * u-boot TEXT base address is. Because the TEXT base resides in the 1137 * boot ROM memory space, to garantee the code can run smoothly after 1138 * that jumping, we must map in the entire boot ROM by Local Access 1139 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1140 * address for boot ROM, such as 0xFE000000. In this case, the default 1141 * LBIU Local Access Widow 0 will not cover this memory space. So, we 1142 * need another window to map in it. 1143 */ 1144 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1145 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1146 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1147 1148 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1149 lis r4, (0x80000012)@h 1150 ori r4, r4, (0x80000012)@l 1151 li r5, CONFIG_SYS_FLASH_SIZE 11521: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1153 addi r4, r4, 1 1154 bne 1b 1155 1156 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1157 blr 1158 1159 /* Though all the LBIU Local Access Windows and LBC Banks will be 1160 * initialized in the C code, we'd better configure boot ROM's 1161 * window 0 and bank 0 correctly at here. 1162 */ 1163remap_flash_by_law0: 1164 /* Initialize the BR0 with the boot ROM starting address. */ 1165 lwz r4, BR0(r3) 1166 li r5, 0x7FFF 1167 and r4, r4, r5 1168 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1169 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1170 or r5, r5, r4 1171 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1172 1173 lwz r4, OR0(r3) 1174 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1175 or r4, r4, r5 1176 stw r4, OR0(r3) 1177 1178 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1179 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1180 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1181 1182 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1183 lis r4, (0x80000012)@h 1184 ori r4, r4, (0x80000012)@l 1185 li r5, CONFIG_SYS_FLASH_SIZE 11861: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1187 addi r4, r4, 1 1188 bne 1b 1189 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1190 1191 1192 xor r4, r4, r4 1193 stw r4, LBLAWBAR1(r3) 1194 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1195 blr 1196#endif /* CONFIG_SYS_FLASHBOOT */ 1197