1 /* 2 * (C) Copyright 2000-2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <mpc83xx.h> 28 #include <command.h> 29 #include <asm/processor.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* ----------------------------------------------------------------- */ 34 35 typedef enum { 36 _unk, 37 _off, 38 _byp, 39 _x8, 40 _x4, 41 _x2, 42 _x1, 43 _1x, 44 _1_5x, 45 _2x, 46 _2_5x, 47 _3x 48 } mult_t; 49 50 typedef struct { 51 mult_t core_csb_ratio; 52 mult_t vco_divider; 53 } corecnf_t; 54 55 corecnf_t corecnf_tab[] = { 56 {_byp, _byp}, /* 0x00 */ 57 {_byp, _byp}, /* 0x01 */ 58 {_byp, _byp}, /* 0x02 */ 59 {_byp, _byp}, /* 0x03 */ 60 {_byp, _byp}, /* 0x04 */ 61 {_byp, _byp}, /* 0x05 */ 62 {_byp, _byp}, /* 0x06 */ 63 {_byp, _byp}, /* 0x07 */ 64 {_1x, _x2}, /* 0x08 */ 65 {_1x, _x4}, /* 0x09 */ 66 {_1x, _x8}, /* 0x0A */ 67 {_1x, _x8}, /* 0x0B */ 68 {_1_5x, _x2}, /* 0x0C */ 69 {_1_5x, _x4}, /* 0x0D */ 70 {_1_5x, _x8}, /* 0x0E */ 71 {_1_5x, _x8}, /* 0x0F */ 72 {_2x, _x2}, /* 0x10 */ 73 {_2x, _x4}, /* 0x11 */ 74 {_2x, _x8}, /* 0x12 */ 75 {_2x, _x8}, /* 0x13 */ 76 {_2_5x, _x2}, /* 0x14 */ 77 {_2_5x, _x4}, /* 0x15 */ 78 {_2_5x, _x8}, /* 0x16 */ 79 {_2_5x, _x8}, /* 0x17 */ 80 {_3x, _x2}, /* 0x18 */ 81 {_3x, _x4}, /* 0x19 */ 82 {_3x, _x8}, /* 0x1A */ 83 {_3x, _x8}, /* 0x1B */ 84 }; 85 86 /* ----------------------------------------------------------------- */ 87 88 /* 89 * 90 */ 91 int get_clocks(void) 92 { 93 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 94 u32 pci_sync_in; 95 u8 spmf; 96 u8 clkin_div; 97 u32 sccr; 98 u32 corecnf_tab_index; 99 u8 corepll; 100 u32 lcrr; 101 102 u32 csb_clk; 103 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 104 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 105 u32 tsec1_clk; 106 u32 tsec2_clk; 107 u32 usbdr_clk; 108 #endif 109 #ifdef CONFIG_MPC834x 110 u32 usbmph_clk; 111 #endif 112 u32 core_clk; 113 u32 i2c1_clk; 114 #if !defined(CONFIG_MPC832x) 115 u32 i2c2_clk; 116 #endif 117 #if defined(CONFIG_MPC8315) 118 u32 tdm_clk; 119 #endif 120 #if defined(CONFIG_FSL_ESDHC) 121 u32 sdhc_clk; 122 #endif 123 u32 enc_clk; 124 u32 lbiu_clk; 125 u32 lclk_clk; 126 u32 mem_clk; 127 #if defined(CONFIG_MPC8360) 128 u32 mem_sec_clk; 129 #endif 130 #if defined(CONFIG_QE) 131 u32 qepmf; 132 u32 qepdf; 133 u32 qe_clk; 134 u32 brg_clk; 135 #endif 136 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 137 defined(CONFIG_MPC837x) 138 u32 pciexp1_clk; 139 u32 pciexp2_clk; 140 #endif 141 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) 142 u32 sata_clk; 143 #endif 144 145 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 146 return -1; 147 148 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); 149 150 if (im->reset.rcwh & HRCWH_PCI_HOST) { 151 #if defined(CONFIG_83XX_CLKIN) 152 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div); 153 #else 154 pci_sync_in = 0xDEADBEEF; 155 #endif 156 } else { 157 #if defined(CONFIG_83XX_PCICLK) 158 pci_sync_in = CONFIG_83XX_PCICLK; 159 #else 160 pci_sync_in = 0xDEADBEEF; 161 #endif 162 } 163 164 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; 165 csb_clk = pci_sync_in * (1 + clkin_div) * spmf; 166 167 sccr = im->clk.sccr; 168 169 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 170 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 171 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { 172 case 0: 173 tsec1_clk = 0; 174 break; 175 case 1: 176 tsec1_clk = csb_clk; 177 break; 178 case 2: 179 tsec1_clk = csb_clk / 2; 180 break; 181 case 3: 182 tsec1_clk = csb_clk / 3; 183 break; 184 default: 185 /* unkown SCCR_TSEC1CM value */ 186 return -2; 187 } 188 #endif 189 190 #if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \ 191 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 192 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { 193 case 0: 194 usbdr_clk = 0; 195 break; 196 case 1: 197 usbdr_clk = csb_clk; 198 break; 199 case 2: 200 usbdr_clk = csb_clk / 2; 201 break; 202 case 3: 203 usbdr_clk = csb_clk / 3; 204 break; 205 default: 206 /* unkown SCCR_USBDRCM value */ 207 return -3; 208 } 209 #endif 210 211 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \ 212 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 213 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { 214 case 0: 215 tsec2_clk = 0; 216 break; 217 case 1: 218 tsec2_clk = csb_clk; 219 break; 220 case 2: 221 tsec2_clk = csb_clk / 2; 222 break; 223 case 3: 224 tsec2_clk = csb_clk / 3; 225 break; 226 default: 227 /* unkown SCCR_TSEC2CM value */ 228 return -4; 229 } 230 #elif defined(CONFIG_MPC8313) 231 tsec2_clk = tsec1_clk; 232 233 if (!(sccr & SCCR_TSEC1ON)) 234 tsec1_clk = 0; 235 if (!(sccr & SCCR_TSEC2ON)) 236 tsec2_clk = 0; 237 #endif 238 239 #if defined(CONFIG_MPC834x) 240 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { 241 case 0: 242 usbmph_clk = 0; 243 break; 244 case 1: 245 usbmph_clk = csb_clk; 246 break; 247 case 2: 248 usbmph_clk = csb_clk / 2; 249 break; 250 case 3: 251 usbmph_clk = csb_clk / 3; 252 break; 253 default: 254 /* unkown SCCR_USBMPHCM value */ 255 return -5; 256 } 257 258 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) { 259 /* if USB MPH clock is not disabled and 260 * USB DR clock is not disabled then 261 * USB MPH & USB DR must have the same rate 262 */ 263 return -6; 264 } 265 #endif 266 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { 267 case 0: 268 enc_clk = 0; 269 break; 270 case 1: 271 enc_clk = csb_clk; 272 break; 273 case 2: 274 enc_clk = csb_clk / 2; 275 break; 276 case 3: 277 enc_clk = csb_clk / 3; 278 break; 279 default: 280 /* unkown SCCR_ENCCM value */ 281 return -7; 282 } 283 284 #if defined(CONFIG_FSL_ESDHC) 285 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) { 286 case 0: 287 sdhc_clk = 0; 288 break; 289 case 1: 290 sdhc_clk = csb_clk; 291 break; 292 case 2: 293 sdhc_clk = csb_clk / 2; 294 break; 295 case 3: 296 sdhc_clk = csb_clk / 3; 297 break; 298 default: 299 /* unkown SCCR_SDHCCM value */ 300 return -8; 301 } 302 #endif 303 #if defined(CONFIG_MPC8315) 304 switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) { 305 case 0: 306 tdm_clk = 0; 307 break; 308 case 1: 309 tdm_clk = csb_clk; 310 break; 311 case 2: 312 tdm_clk = csb_clk / 2; 313 break; 314 case 3: 315 tdm_clk = csb_clk / 3; 316 break; 317 default: 318 /* unkown SCCR_TDMCM value */ 319 return -8; 320 } 321 #endif 322 323 #if defined(CONFIG_MPC834x) 324 i2c1_clk = tsec2_clk; 325 #elif defined(CONFIG_MPC8360) 326 i2c1_clk = csb_clk; 327 #elif defined(CONFIG_MPC832x) 328 i2c1_clk = enc_clk; 329 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) 330 i2c1_clk = enc_clk; 331 #elif defined(CONFIG_FSL_ESDHC) 332 i2c1_clk = sdhc_clk; 333 #elif defined(CONFIG_MPC837x) 334 i2c1_clk = enc_clk; 335 #endif 336 #if !defined(CONFIG_MPC832x) 337 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ 338 #endif 339 340 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 341 defined(CONFIG_MPC837x) 342 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { 343 case 0: 344 pciexp1_clk = 0; 345 break; 346 case 1: 347 pciexp1_clk = csb_clk; 348 break; 349 case 2: 350 pciexp1_clk = csb_clk / 2; 351 break; 352 case 3: 353 pciexp1_clk = csb_clk / 3; 354 break; 355 default: 356 /* unkown SCCR_PCIEXP1CM value */ 357 return -9; 358 } 359 360 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) { 361 case 0: 362 pciexp2_clk = 0; 363 break; 364 case 1: 365 pciexp2_clk = csb_clk; 366 break; 367 case 2: 368 pciexp2_clk = csb_clk / 2; 369 break; 370 case 3: 371 pciexp2_clk = csb_clk / 3; 372 break; 373 default: 374 /* unkown SCCR_PCIEXP2CM value */ 375 return -10; 376 } 377 #endif 378 379 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) 380 switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { 381 case 0: 382 sata_clk = 0; 383 break; 384 case 1: 385 sata_clk = csb_clk; 386 break; 387 case 2: 388 sata_clk = csb_clk / 2; 389 break; 390 case 3: 391 sata_clk = csb_clk / 3; 392 break; 393 default: 394 /* unkown SCCR_SATACM value */ 395 return -11; 396 } 397 #endif 398 399 lbiu_clk = csb_clk * 400 (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT)); 401 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; 402 switch (lcrr) { 403 case 2: 404 case 4: 405 case 8: 406 lclk_clk = lbiu_clk / lcrr; 407 break; 408 default: 409 /* unknown lcrr */ 410 return -12; 411 } 412 413 mem_clk = csb_clk * 414 (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT)); 415 corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT; 416 417 #if defined(CONFIG_MPC8360) 418 mem_sec_clk = csb_clk * (1 + 419 ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT)); 420 #endif 421 422 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); 423 if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) { 424 /* corecnf_tab_index is too high, possibly worng value */ 425 return -11; 426 } 427 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) { 428 case _byp: 429 case _x1: 430 case _1x: 431 core_clk = csb_clk; 432 break; 433 case _1_5x: 434 core_clk = (3 * csb_clk) / 2; 435 break; 436 case _2x: 437 core_clk = 2 * csb_clk; 438 break; 439 case _2_5x: 440 core_clk = (5 * csb_clk) / 2; 441 break; 442 case _3x: 443 core_clk = 3 * csb_clk; 444 break; 445 default: 446 /* unkown core to csb ratio */ 447 return -13; 448 } 449 450 #if defined(CONFIG_QE) 451 qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT; 452 qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT; 453 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); 454 brg_clk = qe_clk / 2; 455 #endif 456 457 gd->csb_clk = csb_clk; 458 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 459 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 460 gd->tsec1_clk = tsec1_clk; 461 gd->tsec2_clk = tsec2_clk; 462 gd->usbdr_clk = usbdr_clk; 463 #endif 464 #if defined(CONFIG_MPC834x) 465 gd->usbmph_clk = usbmph_clk; 466 #endif 467 #if defined(CONFIG_MPC8315) 468 gd->tdm_clk = tdm_clk; 469 #endif 470 #if defined(CONFIG_FSL_ESDHC) 471 gd->sdhc_clk = sdhc_clk; 472 #endif 473 gd->core_clk = core_clk; 474 gd->i2c1_clk = i2c1_clk; 475 #if !defined(CONFIG_MPC832x) 476 gd->i2c2_clk = i2c2_clk; 477 #endif 478 gd->enc_clk = enc_clk; 479 gd->lbiu_clk = lbiu_clk; 480 gd->lclk_clk = lclk_clk; 481 gd->mem_clk = mem_clk; 482 #if defined(CONFIG_MPC8360) 483 gd->mem_sec_clk = mem_sec_clk; 484 #endif 485 #if defined(CONFIG_QE) 486 gd->qe_clk = qe_clk; 487 gd->brg_clk = brg_clk; 488 #endif 489 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 490 defined(CONFIG_MPC837x) 491 gd->pciexp1_clk = pciexp1_clk; 492 gd->pciexp2_clk = pciexp2_clk; 493 #endif 494 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) 495 gd->sata_clk = sata_clk; 496 #endif 497 gd->pci_clk = pci_sync_in; 498 gd->cpu_clk = gd->core_clk; 499 gd->bus_clk = gd->csb_clk; 500 return 0; 501 502 } 503 504 /******************************************** 505 * get_bus_freq 506 * return system bus freq in Hz 507 *********************************************/ 508 ulong get_bus_freq(ulong dummy) 509 { 510 return gd->csb_clk; 511 } 512 513 /******************************************** 514 * get_ddr_freq 515 * return ddr bus freq in Hz 516 *********************************************/ 517 ulong get_ddr_freq(ulong dummy) 518 { 519 return gd->mem_clk; 520 } 521 522 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) 523 { 524 char buf[32]; 525 526 printf("Clock configuration:\n"); 527 printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk)); 528 printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk)); 529 #if defined(CONFIG_QE) 530 printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk)); 531 printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk)); 532 #endif 533 printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk)); 534 printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk)); 535 printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk)); 536 #if defined(CONFIG_MPC8360) 537 printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk)); 538 #endif 539 printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk)); 540 printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk)); 541 #if !defined(CONFIG_MPC832x) 542 printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk)); 543 #endif 544 #if defined(CONFIG_MPC8315) 545 printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk)); 546 #endif 547 #if defined(CONFIG_FSL_ESDHC) 548 printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk)); 549 #endif 550 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 551 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 552 printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk)); 553 printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk)); 554 printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk)); 555 #endif 556 #if defined(CONFIG_MPC834x) 557 printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk)); 558 #endif 559 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 560 defined(CONFIG_MPC837x) 561 printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk)); 562 printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk)); 563 #endif 564 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) 565 printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk)); 566 #endif 567 return 0; 568 } 569 570 U_BOOT_CMD(clocks, 1, 0, do_clocks, 571 "print clock configuration", 572 " clocks" 573 ); 574