183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2a47a12beSStefan Roese /* 3a47a12beSStefan Roese * Freescale SerDes initialization routine 4a47a12beSStefan Roese * 5a6cdaa0cSTimur Tabi * Copyright 2007,2011 Freescale Semiconductor, Inc. 6a47a12beSStefan Roese * Copyright (C) 2008 MontaVista Software, Inc. 7a47a12beSStefan Roese * 8a47a12beSStefan Roese * Author: Li Yang <leoli@freescale.com> 9a47a12beSStefan Roese */ 10a47a12beSStefan Roese 11*d2166319SMario Six #ifndef CONFIG_MPC83XX_SERDES 12*d2166319SMario Six 13a47a12beSStefan Roese #include <config.h> 14a47a12beSStefan Roese #include <common.h> 15a47a12beSStefan Roese #include <asm/io.h> 167e1afb62SKumar Gala #include <asm/fsl_mpc83xx_serdes.h> 17a47a12beSStefan Roese 18a47a12beSStefan Roese /* SerDes registers */ 19a47a12beSStefan Roese #define FSL_SRDSCR0_OFFS 0x0 20a47a12beSStefan Roese #define FSL_SRDSCR0_DPP_1V2 0x00008800 21509adc8bSJerry Huang #define FSL_SRDSCR0_TXEQA_MASK 0x00007000 22509adc8bSJerry Huang #define FSL_SRDSCR0_TXEQA_SATA 0x00001000 23509adc8bSJerry Huang #define FSL_SRDSCR0_TXEQE_MASK 0x00000700 24509adc8bSJerry Huang #define FSL_SRDSCR0_TXEQE_SATA 0x00000100 25a47a12beSStefan Roese #define FSL_SRDSCR1_OFFS 0x4 26a47a12beSStefan Roese #define FSL_SRDSCR1_PLLBW 0x00000040 27a47a12beSStefan Roese #define FSL_SRDSCR2_OFFS 0x8 28a47a12beSStefan Roese #define FSL_SRDSCR2_VDD_1V2 0x00800000 29a47a12beSStefan Roese #define FSL_SRDSCR2_SEIC_MASK 0x00001c1c 30a47a12beSStefan Roese #define FSL_SRDSCR2_SEIC_SATA 0x00001414 31a47a12beSStefan Roese #define FSL_SRDSCR2_SEIC_PEX 0x00001010 32a47a12beSStefan Roese #define FSL_SRDSCR2_SEIC_SGMII 0x00000101 33a47a12beSStefan Roese #define FSL_SRDSCR3_OFFS 0xc 34a47a12beSStefan Roese #define FSL_SRDSCR3_KFR_SATA 0x10100000 35a47a12beSStefan Roese #define FSL_SRDSCR3_KPH_SATA 0x04040000 36a47a12beSStefan Roese #define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000 37a47a12beSStefan Roese #define FSL_SRDSCR3_SDTXL_SATA 0x00000505 38a47a12beSStefan Roese #define FSL_SRDSCR4_OFFS 0x10 39a47a12beSStefan Roese #define FSL_SRDSCR4_PROT_SATA 0x00000808 40a47a12beSStefan Roese #define FSL_SRDSCR4_PROT_PEX 0x00000101 41a47a12beSStefan Roese #define FSL_SRDSCR4_PROT_SGMII 0x00000505 42a47a12beSStefan Roese #define FSL_SRDSCR4_PLANE_X2 0x01000000 43a47a12beSStefan Roese #define FSL_SRDSRSTCTL_OFFS 0x20 44a47a12beSStefan Roese #define FSL_SRDSRSTCTL_RST 0x80000000 45a47a12beSStefan Roese #define FSL_SRDSRSTCTL_SATA_RESET 0xf 46a47a12beSStefan Roese 47a47a12beSStefan Roese void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) 48a47a12beSStefan Roese { 49a47a12beSStefan Roese void *regs = (void *)CONFIG_SYS_IMMR + offset; 50a47a12beSStefan Roese u32 tmp; 51a47a12beSStefan Roese 52a47a12beSStefan Roese /* 1.0V corevdd */ 53a47a12beSStefan Roese if (vdd) { 54a47a12beSStefan Roese /* DPPE/DPPA = 0 */ 55a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR0_OFFS); 56a47a12beSStefan Roese tmp &= ~FSL_SRDSCR0_DPP_1V2; 57a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR0_OFFS, tmp); 58a47a12beSStefan Roese 59a47a12beSStefan Roese /* VDD = 0 */ 60a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR2_OFFS); 61a47a12beSStefan Roese tmp &= ~FSL_SRDSCR2_VDD_1V2; 62a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR2_OFFS, tmp); 63a47a12beSStefan Roese } 64a47a12beSStefan Roese 65a47a12beSStefan Roese /* protocol specific configuration */ 66a47a12beSStefan Roese switch (proto) { 67a47a12beSStefan Roese case FSL_SERDES_PROTO_SATA: 68a47a12beSStefan Roese /* Set and clear reset bits */ 69a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); 70a47a12beSStefan Roese tmp |= FSL_SRDSRSTCTL_SATA_RESET; 71a47a12beSStefan Roese out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); 72a47a12beSStefan Roese udelay(1000); 73a47a12beSStefan Roese tmp &= ~FSL_SRDSRSTCTL_SATA_RESET; 74a47a12beSStefan Roese out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); 75a47a12beSStefan Roese 76509adc8bSJerry Huang /* Configure SRDSCR0 */ 77509adc8bSJerry Huang clrsetbits_be32(regs + FSL_SRDSCR0_OFFS, 78509adc8bSJerry Huang FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK, 79509adc8bSJerry Huang FSL_SRDSCR0_TXEQA_SATA | FSL_SRDSCR0_TXEQE_SATA); 80509adc8bSJerry Huang 81a47a12beSStefan Roese /* Configure SRDSCR1 */ 82a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR1_OFFS); 83a47a12beSStefan Roese tmp &= ~FSL_SRDSCR1_PLLBW; 84a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR1_OFFS, tmp); 85a47a12beSStefan Roese 86a47a12beSStefan Roese /* Configure SRDSCR2 */ 87a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR2_OFFS); 88a47a12beSStefan Roese tmp &= ~FSL_SRDSCR2_SEIC_MASK; 89a47a12beSStefan Roese tmp |= FSL_SRDSCR2_SEIC_SATA; 90a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR2_OFFS, tmp); 91a47a12beSStefan Roese 92a47a12beSStefan Roese /* Configure SRDSCR3 */ 93a47a12beSStefan Roese tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA | 94a47a12beSStefan Roese FSL_SRDSCR3_SDFM_SATA_PEX | 95a47a12beSStefan Roese FSL_SRDSCR3_SDTXL_SATA; 96a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR3_OFFS, tmp); 97a47a12beSStefan Roese 98a47a12beSStefan Roese /* Configure SRDSCR4 */ 99a47a12beSStefan Roese tmp = rfcks | FSL_SRDSCR4_PROT_SATA; 100a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR4_OFFS, tmp); 101a47a12beSStefan Roese break; 102a47a12beSStefan Roese case FSL_SERDES_PROTO_PEX: 103a47a12beSStefan Roese case FSL_SERDES_PROTO_PEX_X2: 104a47a12beSStefan Roese /* Configure SRDSCR1 */ 105a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR1_OFFS); 106a47a12beSStefan Roese tmp |= FSL_SRDSCR1_PLLBW; 107a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR1_OFFS, tmp); 108a47a12beSStefan Roese 109a47a12beSStefan Roese /* Configure SRDSCR2 */ 110a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR2_OFFS); 111a47a12beSStefan Roese tmp &= ~FSL_SRDSCR2_SEIC_MASK; 112a47a12beSStefan Roese tmp |= FSL_SRDSCR2_SEIC_PEX; 113a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR2_OFFS, tmp); 114a47a12beSStefan Roese 115a47a12beSStefan Roese /* Configure SRDSCR3 */ 116a47a12beSStefan Roese tmp = FSL_SRDSCR3_SDFM_SATA_PEX; 117a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR3_OFFS, tmp); 118a47a12beSStefan Roese 119a47a12beSStefan Roese /* Configure SRDSCR4 */ 120a47a12beSStefan Roese tmp = rfcks | FSL_SRDSCR4_PROT_PEX; 121a47a12beSStefan Roese if (proto == FSL_SERDES_PROTO_PEX_X2) 122a47a12beSStefan Roese tmp |= FSL_SRDSCR4_PLANE_X2; 123a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR4_OFFS, tmp); 124a47a12beSStefan Roese break; 125a47a12beSStefan Roese case FSL_SERDES_PROTO_SGMII: 126a47a12beSStefan Roese /* Configure SRDSCR1 */ 127a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR1_OFFS); 128a47a12beSStefan Roese tmp &= ~FSL_SRDSCR1_PLLBW; 129a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR1_OFFS, tmp); 130a47a12beSStefan Roese 131a47a12beSStefan Roese /* Configure SRDSCR2 */ 132a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR2_OFFS); 133a47a12beSStefan Roese tmp &= ~FSL_SRDSCR2_SEIC_MASK; 134a47a12beSStefan Roese tmp |= FSL_SRDSCR2_SEIC_SGMII; 135a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR2_OFFS, tmp); 136a47a12beSStefan Roese 137a47a12beSStefan Roese /* Configure SRDSCR3 */ 138a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR3_OFFS, 0); 139a47a12beSStefan Roese 140a47a12beSStefan Roese /* Configure SRDSCR4 */ 141a47a12beSStefan Roese tmp = rfcks | FSL_SRDSCR4_PROT_SGMII; 142a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR4_OFFS, tmp); 143a47a12beSStefan Roese break; 144a47a12beSStefan Roese default: 145a47a12beSStefan Roese return; 146a47a12beSStefan Roese } 147a47a12beSStefan Roese 148a47a12beSStefan Roese /* Do a software reset */ 149a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); 150a47a12beSStefan Roese tmp |= FSL_SRDSRSTCTL_RST; 151a47a12beSStefan Roese out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); 152a47a12beSStefan Roese } 153*d2166319SMario Six 154*d2166319SMario Six #endif /* !CONFIG_MPC83XX_SERDES */ 155