1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * Freescale SerDes initialization routine 3a47a12beSStefan Roese * 4a47a12beSStefan Roese * Copyright (C) 2007 Freescale Semicondutor, Inc. 5a47a12beSStefan Roese * Copyright (C) 2008 MontaVista Software, Inc. 6a47a12beSStefan Roese * 7a47a12beSStefan Roese * Author: Li Yang <leoli@freescale.com> 8a47a12beSStefan Roese * 9a47a12beSStefan Roese * This program is free software; you can redistribute it and/or modify it 10a47a12beSStefan Roese * under the terms of the GNU General Public License as published by the 11a47a12beSStefan Roese * Free Software Foundation; either version 2 of the License, or (at your 12a47a12beSStefan Roese * option) any later version. 13a47a12beSStefan Roese */ 14a47a12beSStefan Roese 15a47a12beSStefan Roese #include <config.h> 16a47a12beSStefan Roese #include <common.h> 17a47a12beSStefan Roese #include <asm/io.h> 18*7e1afb62SKumar Gala #include <asm/fsl_mpc83xx_serdes.h> 19a47a12beSStefan Roese 20a47a12beSStefan Roese /* SerDes registers */ 21a47a12beSStefan Roese #define FSL_SRDSCR0_OFFS 0x0 22a47a12beSStefan Roese #define FSL_SRDSCR0_DPP_1V2 0x00008800 23a47a12beSStefan Roese #define FSL_SRDSCR1_OFFS 0x4 24a47a12beSStefan Roese #define FSL_SRDSCR1_PLLBW 0x00000040 25a47a12beSStefan Roese #define FSL_SRDSCR2_OFFS 0x8 26a47a12beSStefan Roese #define FSL_SRDSCR2_VDD_1V2 0x00800000 27a47a12beSStefan Roese #define FSL_SRDSCR2_SEIC_MASK 0x00001c1c 28a47a12beSStefan Roese #define FSL_SRDSCR2_SEIC_SATA 0x00001414 29a47a12beSStefan Roese #define FSL_SRDSCR2_SEIC_PEX 0x00001010 30a47a12beSStefan Roese #define FSL_SRDSCR2_SEIC_SGMII 0x00000101 31a47a12beSStefan Roese #define FSL_SRDSCR3_OFFS 0xc 32a47a12beSStefan Roese #define FSL_SRDSCR3_KFR_SATA 0x10100000 33a47a12beSStefan Roese #define FSL_SRDSCR3_KPH_SATA 0x04040000 34a47a12beSStefan Roese #define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000 35a47a12beSStefan Roese #define FSL_SRDSCR3_SDTXL_SATA 0x00000505 36a47a12beSStefan Roese #define FSL_SRDSCR4_OFFS 0x10 37a47a12beSStefan Roese #define FSL_SRDSCR4_PROT_SATA 0x00000808 38a47a12beSStefan Roese #define FSL_SRDSCR4_PROT_PEX 0x00000101 39a47a12beSStefan Roese #define FSL_SRDSCR4_PROT_SGMII 0x00000505 40a47a12beSStefan Roese #define FSL_SRDSCR4_PLANE_X2 0x01000000 41a47a12beSStefan Roese #define FSL_SRDSRSTCTL_OFFS 0x20 42a47a12beSStefan Roese #define FSL_SRDSRSTCTL_RST 0x80000000 43a47a12beSStefan Roese #define FSL_SRDSRSTCTL_SATA_RESET 0xf 44a47a12beSStefan Roese 45a47a12beSStefan Roese void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) 46a47a12beSStefan Roese { 47a47a12beSStefan Roese void *regs = (void *)CONFIG_SYS_IMMR + offset; 48a47a12beSStefan Roese u32 tmp; 49a47a12beSStefan Roese 50a47a12beSStefan Roese /* 1.0V corevdd */ 51a47a12beSStefan Roese if (vdd) { 52a47a12beSStefan Roese /* DPPE/DPPA = 0 */ 53a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR0_OFFS); 54a47a12beSStefan Roese tmp &= ~FSL_SRDSCR0_DPP_1V2; 55a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR0_OFFS, tmp); 56a47a12beSStefan Roese 57a47a12beSStefan Roese /* VDD = 0 */ 58a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR2_OFFS); 59a47a12beSStefan Roese tmp &= ~FSL_SRDSCR2_VDD_1V2; 60a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR2_OFFS, tmp); 61a47a12beSStefan Roese } 62a47a12beSStefan Roese 63a47a12beSStefan Roese /* protocol specific configuration */ 64a47a12beSStefan Roese switch (proto) { 65a47a12beSStefan Roese case FSL_SERDES_PROTO_SATA: 66a47a12beSStefan Roese /* Set and clear reset bits */ 67a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); 68a47a12beSStefan Roese tmp |= FSL_SRDSRSTCTL_SATA_RESET; 69a47a12beSStefan Roese out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); 70a47a12beSStefan Roese udelay(1000); 71a47a12beSStefan Roese tmp &= ~FSL_SRDSRSTCTL_SATA_RESET; 72a47a12beSStefan Roese out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); 73a47a12beSStefan Roese 74a47a12beSStefan Roese /* Configure SRDSCR1 */ 75a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR1_OFFS); 76a47a12beSStefan Roese tmp &= ~FSL_SRDSCR1_PLLBW; 77a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR1_OFFS, tmp); 78a47a12beSStefan Roese 79a47a12beSStefan Roese /* Configure SRDSCR2 */ 80a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR2_OFFS); 81a47a12beSStefan Roese tmp &= ~FSL_SRDSCR2_SEIC_MASK; 82a47a12beSStefan Roese tmp |= FSL_SRDSCR2_SEIC_SATA; 83a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR2_OFFS, tmp); 84a47a12beSStefan Roese 85a47a12beSStefan Roese /* Configure SRDSCR3 */ 86a47a12beSStefan Roese tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA | 87a47a12beSStefan Roese FSL_SRDSCR3_SDFM_SATA_PEX | 88a47a12beSStefan Roese FSL_SRDSCR3_SDTXL_SATA; 89a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR3_OFFS, tmp); 90a47a12beSStefan Roese 91a47a12beSStefan Roese /* Configure SRDSCR4 */ 92a47a12beSStefan Roese tmp = rfcks | FSL_SRDSCR4_PROT_SATA; 93a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR4_OFFS, tmp); 94a47a12beSStefan Roese break; 95a47a12beSStefan Roese case FSL_SERDES_PROTO_PEX: 96a47a12beSStefan Roese case FSL_SERDES_PROTO_PEX_X2: 97a47a12beSStefan Roese /* Configure SRDSCR1 */ 98a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR1_OFFS); 99a47a12beSStefan Roese tmp |= FSL_SRDSCR1_PLLBW; 100a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR1_OFFS, tmp); 101a47a12beSStefan Roese 102a47a12beSStefan Roese /* Configure SRDSCR2 */ 103a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR2_OFFS); 104a47a12beSStefan Roese tmp &= ~FSL_SRDSCR2_SEIC_MASK; 105a47a12beSStefan Roese tmp |= FSL_SRDSCR2_SEIC_PEX; 106a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR2_OFFS, tmp); 107a47a12beSStefan Roese 108a47a12beSStefan Roese /* Configure SRDSCR3 */ 109a47a12beSStefan Roese tmp = FSL_SRDSCR3_SDFM_SATA_PEX; 110a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR3_OFFS, tmp); 111a47a12beSStefan Roese 112a47a12beSStefan Roese /* Configure SRDSCR4 */ 113a47a12beSStefan Roese tmp = rfcks | FSL_SRDSCR4_PROT_PEX; 114a47a12beSStefan Roese if (proto == FSL_SERDES_PROTO_PEX_X2) 115a47a12beSStefan Roese tmp |= FSL_SRDSCR4_PLANE_X2; 116a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR4_OFFS, tmp); 117a47a12beSStefan Roese break; 118a47a12beSStefan Roese case FSL_SERDES_PROTO_SGMII: 119a47a12beSStefan Roese /* Configure SRDSCR1 */ 120a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR1_OFFS); 121a47a12beSStefan Roese tmp &= ~FSL_SRDSCR1_PLLBW; 122a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR1_OFFS, tmp); 123a47a12beSStefan Roese 124a47a12beSStefan Roese /* Configure SRDSCR2 */ 125a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSCR2_OFFS); 126a47a12beSStefan Roese tmp &= ~FSL_SRDSCR2_SEIC_MASK; 127a47a12beSStefan Roese tmp |= FSL_SRDSCR2_SEIC_SGMII; 128a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR2_OFFS, tmp); 129a47a12beSStefan Roese 130a47a12beSStefan Roese /* Configure SRDSCR3 */ 131a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR3_OFFS, 0); 132a47a12beSStefan Roese 133a47a12beSStefan Roese /* Configure SRDSCR4 */ 134a47a12beSStefan Roese tmp = rfcks | FSL_SRDSCR4_PROT_SGMII; 135a47a12beSStefan Roese out_be32(regs + FSL_SRDSCR4_OFFS, tmp); 136a47a12beSStefan Roese break; 137a47a12beSStefan Roese default: 138a47a12beSStefan Roese return; 139a47a12beSStefan Roese } 140a47a12beSStefan Roese 141a47a12beSStefan Roese /* Do a software reset */ 142a47a12beSStefan Roese tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); 143a47a12beSStefan Roese tmp |= FSL_SRDSRSTCTL_RST; 144a47a12beSStefan Roese out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); 145a47a12beSStefan Roese } 146