1*4c835a60SStefan Roese // SPDX-License-Identifier: GPL-2.0+ 2*4c835a60SStefan Roese /* 3*4c835a60SStefan Roese * Copyright (C) 2018 Stefan Roese <sr@denx.de> 4*4c835a60SStefan Roese */ 5*4c835a60SStefan Roese 6*4c835a60SStefan Roese #include <common.h> 7*4c835a60SStefan Roese #include <dm.h> 8*4c835a60SStefan Roese #include <ram.h> 9*4c835a60SStefan Roese #include <asm/io.h> 10*4c835a60SStefan Roese #include <linux/io.h> 11*4c835a60SStefan Roese #include <linux/sizes.h> 12*4c835a60SStefan Roese #include "mt76xx.h" 13*4c835a60SStefan Roese 14*4c835a60SStefan Roese #define STR_LEN 6 15*4c835a60SStefan Roese 16*4c835a60SStefan Roese #ifdef CONFIG_BOOT_ROM 17*4c835a60SStefan Roese int mach_cpu_init(void) 18*4c835a60SStefan Roese { 19*4c835a60SStefan Roese ddr_calibrate(); 20*4c835a60SStefan Roese 21*4c835a60SStefan Roese return 0; 22*4c835a60SStefan Roese } 23*4c835a60SStefan Roese #endif 24*4c835a60SStefan Roese 25*4c835a60SStefan Roese int dram_init(void) 26*4c835a60SStefan Roese { 27*4c835a60SStefan Roese gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M); 28*4c835a60SStefan Roese 29*4c835a60SStefan Roese return 0; 30*4c835a60SStefan Roese } 31*4c835a60SStefan Roese 32*4c835a60SStefan Roese int print_cpuinfo(void) 33*4c835a60SStefan Roese { 34*4c835a60SStefan Roese static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)", 35*4c835a60SStefan Roese "PLL (4-Byte SPI Addr)", 36*4c835a60SStefan Roese "XTAL (3-Byte SPI Addr)", 37*4c835a60SStefan Roese "XTAL (4-Byte SPI Addr)" }; 38*4c835a60SStefan Roese const void *blob = gd->fdt_blob; 39*4c835a60SStefan Roese void __iomem *sysc_base; 40*4c835a60SStefan Roese char buf[STR_LEN + 1]; 41*4c835a60SStefan Roese fdt_addr_t base; 42*4c835a60SStefan Roese fdt_size_t size; 43*4c835a60SStefan Roese char *str; 44*4c835a60SStefan Roese int node; 45*4c835a60SStefan Roese u32 val; 46*4c835a60SStefan Roese 47*4c835a60SStefan Roese /* Get system controller base address */ 48*4c835a60SStefan Roese node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc"); 49*4c835a60SStefan Roese if (node < 0) 50*4c835a60SStefan Roese return -FDT_ERR_NOTFOUND; 51*4c835a60SStefan Roese 52*4c835a60SStefan Roese base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg", 53*4c835a60SStefan Roese 0, &size, true); 54*4c835a60SStefan Roese if (base == FDT_ADDR_T_NONE) 55*4c835a60SStefan Roese return -EINVAL; 56*4c835a60SStefan Roese 57*4c835a60SStefan Roese sysc_base = ioremap_nocache(base, size); 58*4c835a60SStefan Roese 59*4c835a60SStefan Roese str = (char *)sysc_base + MT76XX_CHIPID_OFFS; 60*4c835a60SStefan Roese snprintf(buf, STR_LEN + 1, "%s", str); 61*4c835a60SStefan Roese val = readl(sysc_base + MT76XX_CHIP_REV_ID_OFFS); 62*4c835a60SStefan Roese printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf, 63*4c835a60SStefan Roese (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0)); 64*4c835a60SStefan Roese 65*4c835a60SStefan Roese val = (readl(sysc_base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1; 66*4c835a60SStefan Roese printf("Boot from %s\n", boot_str[val]); 67*4c835a60SStefan Roese 68*4c835a60SStefan Roese return 0; 69*4c835a60SStefan Roese } 70