1*83d290c5STom Rini// SPDX-License-Identifier: GPL-2.0+ 2be961fa1SPurna Chandra Mandal/* 3be961fa1SPurna Chandra Mandal * Copyright 2015 Microchip Technology, Inc. 4be961fa1SPurna Chandra Mandal * Purna Chandra Mandal, <purna.mandal@microchip.com> 5be961fa1SPurna Chandra Mandal */ 6be961fa1SPurna Chandra Mandal 7be961fa1SPurna Chandra Mandal#include <dt-bindings/interrupt-controller/irq.h> 8be961fa1SPurna Chandra Mandal#include <dt-bindings/clock/microchip,clock.h> 9be961fa1SPurna Chandra Mandal#include <dt-bindings/gpio/gpio.h> 10be961fa1SPurna Chandra Mandal#include "skeleton.dtsi" 11be961fa1SPurna Chandra Mandal 12be961fa1SPurna Chandra Mandal/ { 13be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda", "microchip,pic32mz"; 14be961fa1SPurna Chandra Mandal 15be961fa1SPurna Chandra Mandal aliases { 16be961fa1SPurna Chandra Mandal gpio0 = &gpioA; 17be961fa1SPurna Chandra Mandal gpio1 = &gpioB; 18be961fa1SPurna Chandra Mandal gpio2 = &gpioC; 19be961fa1SPurna Chandra Mandal gpio3 = &gpioD; 20be961fa1SPurna Chandra Mandal gpio4 = &gpioE; 21be961fa1SPurna Chandra Mandal gpio5 = &gpioF; 22be961fa1SPurna Chandra Mandal gpio6 = &gpioG; 23be961fa1SPurna Chandra Mandal gpio7 = &gpioH; 24be961fa1SPurna Chandra Mandal gpio8 = &gpioJ; 25be961fa1SPurna Chandra Mandal gpio9 = &gpioK; 26be961fa1SPurna Chandra Mandal }; 27be961fa1SPurna Chandra Mandal 28be961fa1SPurna Chandra Mandal cpus { 29be961fa1SPurna Chandra Mandal cpu@0 { 30be961fa1SPurna Chandra Mandal compatible = "mips,mips14kc"; 31be961fa1SPurna Chandra Mandal }; 32be961fa1SPurna Chandra Mandal }; 33be961fa1SPurna Chandra Mandal 34be961fa1SPurna Chandra Mandal clock: clk@1f801200 { 35be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-clk"; 36be961fa1SPurna Chandra Mandal reg = <0x1f801200 0x1000>; 37be961fa1SPurna Chandra Mandal #clock-cells = <1>; 38be961fa1SPurna Chandra Mandal }; 39be961fa1SPurna Chandra Mandal 40be961fa1SPurna Chandra Mandal uart1: serial@1f822000 { 41be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-uart"; 42be961fa1SPurna Chandra Mandal reg = <0x1f822000 0x50>; 43be961fa1SPurna Chandra Mandal interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; 44be961fa1SPurna Chandra Mandal status = "disabled"; 45be961fa1SPurna Chandra Mandal clocks = <&clock PB2CLK>; 46be961fa1SPurna Chandra Mandal }; 47be961fa1SPurna Chandra Mandal 48be961fa1SPurna Chandra Mandal uart2: serial@1f822200 { 49be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-uart"; 50be961fa1SPurna Chandra Mandal reg = <0x1f822200 0x50>; 51be961fa1SPurna Chandra Mandal interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; 52be961fa1SPurna Chandra Mandal clocks = <&clock PB2CLK>; 53be961fa1SPurna Chandra Mandal status = "disabled"; 54be961fa1SPurna Chandra Mandal }; 55be961fa1SPurna Chandra Mandal 56be961fa1SPurna Chandra Mandal uart6: serial@1f822a00 { 57be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-uart"; 58be961fa1SPurna Chandra Mandal reg = <0x1f822a00 0x50>; 59be961fa1SPurna Chandra Mandal interrupts = <188 IRQ_TYPE_LEVEL_HIGH>; 60be961fa1SPurna Chandra Mandal clocks = <&clock PB2CLK>; 61be961fa1SPurna Chandra Mandal status = "disabled"; 62be961fa1SPurna Chandra Mandal }; 63be961fa1SPurna Chandra Mandal 64be961fa1SPurna Chandra Mandal evic: interrupt-controller@1f810000 { 65be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-evic"; 66be961fa1SPurna Chandra Mandal interrupt-controller; 67be961fa1SPurna Chandra Mandal #interrupt-cells = <2>; 68be961fa1SPurna Chandra Mandal reg = <0x1f810000 0x1000>; 69be961fa1SPurna Chandra Mandal }; 70be961fa1SPurna Chandra Mandal 71be961fa1SPurna Chandra Mandal pinctrl: pinctrl@1f801400 { 72be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-pinctrl"; 73be961fa1SPurna Chandra Mandal reg = <0x1f801400 0x100>, /* in */ 74be961fa1SPurna Chandra Mandal <0x1f801500 0x200>, /* out */ 75be961fa1SPurna Chandra Mandal <0x1f860000 0xa00>; /* port */ 76be961fa1SPurna Chandra Mandal reg-names = "ppsin","ppsout","port"; 77be961fa1SPurna Chandra Mandal status = "disabled"; 78be961fa1SPurna Chandra Mandal 79be961fa1SPurna Chandra Mandal ranges = <0 0x1f860000 0xa00>; 80be961fa1SPurna Chandra Mandal #address-cells = <1>; 81be961fa1SPurna Chandra Mandal #size-cells = <1>; 82be961fa1SPurna Chandra Mandal gpioA: gpio0@0 { 83be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-gpio"; 84be961fa1SPurna Chandra Mandal reg = <0x000 0x48>; 85be961fa1SPurna Chandra Mandal gpio-controller; 86be961fa1SPurna Chandra Mandal #gpio-cells = <2>; 87be961fa1SPurna Chandra Mandal }; 88be961fa1SPurna Chandra Mandal 89be961fa1SPurna Chandra Mandal gpioB: gpio1@100 { 90be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-gpio"; 91be961fa1SPurna Chandra Mandal reg = <0x100 0x48>; 92be961fa1SPurna Chandra Mandal gpio-controller; 93be961fa1SPurna Chandra Mandal #gpio-cells = <2>; 94be961fa1SPurna Chandra Mandal }; 95be961fa1SPurna Chandra Mandal 96be961fa1SPurna Chandra Mandal gpioC: gpio2@200 { 97be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-gpio"; 98be961fa1SPurna Chandra Mandal reg = <0x200 0x48>; 99be961fa1SPurna Chandra Mandal gpio-controller; 100be961fa1SPurna Chandra Mandal #gpio-cells = <2>; 101be961fa1SPurna Chandra Mandal }; 102be961fa1SPurna Chandra Mandal 103be961fa1SPurna Chandra Mandal gpioD: gpio3@300 { 104be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-gpio"; 105be961fa1SPurna Chandra Mandal reg = <0x300 0x48>; 106be961fa1SPurna Chandra Mandal gpio-controller; 107be961fa1SPurna Chandra Mandal #gpio-cells = <2>; 108be961fa1SPurna Chandra Mandal }; 109be961fa1SPurna Chandra Mandal 110be961fa1SPurna Chandra Mandal gpioE: gpio4@400 { 111be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-gpio"; 112be961fa1SPurna Chandra Mandal reg = <0x400 0x48>; 113be961fa1SPurna Chandra Mandal gpio-controller; 114be961fa1SPurna Chandra Mandal #gpio-cells = <2>; 115be961fa1SPurna Chandra Mandal }; 116be961fa1SPurna Chandra Mandal 117be961fa1SPurna Chandra Mandal gpioF: gpio5@500 { 118be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-gpio"; 119be961fa1SPurna Chandra Mandal reg = <0x500 0x48>; 120be961fa1SPurna Chandra Mandal gpio-controller; 121be961fa1SPurna Chandra Mandal #gpio-cells = <2>; 122be961fa1SPurna Chandra Mandal }; 123be961fa1SPurna Chandra Mandal 124be961fa1SPurna Chandra Mandal gpioG: gpio6@600 { 125be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-gpio"; 126be961fa1SPurna Chandra Mandal reg = <0x600 0x48>; 127be961fa1SPurna Chandra Mandal gpio-controller; 128be961fa1SPurna Chandra Mandal #gpio-cells = <2>; 129be961fa1SPurna Chandra Mandal }; 130be961fa1SPurna Chandra Mandal 131be961fa1SPurna Chandra Mandal gpioH: gpio7@700 { 132be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-gpio"; 133be961fa1SPurna Chandra Mandal reg = <0x700 0x48>; 134be961fa1SPurna Chandra Mandal gpio-controller; 135be961fa1SPurna Chandra Mandal #gpio-cells = <2>; 136be961fa1SPurna Chandra Mandal }; 137be961fa1SPurna Chandra Mandal 138be961fa1SPurna Chandra Mandal gpioJ: gpio8@800 { 139be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-gpio"; 140be961fa1SPurna Chandra Mandal reg = <0x800 0x48>; 141be961fa1SPurna Chandra Mandal gpio-controller; 142be961fa1SPurna Chandra Mandal #gpio-cells = <2>; 143be961fa1SPurna Chandra Mandal }; 144be961fa1SPurna Chandra Mandal 145be961fa1SPurna Chandra Mandal gpioK: gpio9@900 { 146be961fa1SPurna Chandra Mandal compatible = "microchip,pic32mzda-gpio"; 147be961fa1SPurna Chandra Mandal reg = <0x900 0x48>; 148be961fa1SPurna Chandra Mandal gpio-controller; 149be961fa1SPurna Chandra Mandal #gpio-cells = <2>; 150be961fa1SPurna Chandra Mandal }; 151be961fa1SPurna Chandra Mandal }; 152c76eb72cSPurna Chandra Mandal 153c76eb72cSPurna Chandra Mandal sdhci: sdhci@1f8ec000 { 154c76eb72cSPurna Chandra Mandal compatible = "microchip,pic32mzda-sdhci"; 155c76eb72cSPurna Chandra Mandal reg = <0x1f8ec000 0x100>; 156c76eb72cSPurna Chandra Mandal interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; 157c76eb72cSPurna Chandra Mandal clocks = <&clock REF4CLK>, <&clock PB5CLK>; 158c76eb72cSPurna Chandra Mandal clock-names = "base_clk", "sys_clk"; 159c76eb72cSPurna Chandra Mandal clock-freq-min-max = <25000000>,<25000000>; 160c76eb72cSPurna Chandra Mandal bus-width = <4>; 161c76eb72cSPurna Chandra Mandal status = "disabled"; 162c76eb72cSPurna Chandra Mandal }; 1637d514a74SPurna Chandra Mandal 1647d514a74SPurna Chandra Mandal ethernet: ethernet@1f882000 { 1657d514a74SPurna Chandra Mandal compatible = "microchip,pic32mzda-eth"; 1667d514a74SPurna Chandra Mandal reg = <0x1f882000 0x1000>; 1677d514a74SPurna Chandra Mandal interrupts = <153 IRQ_TYPE_LEVEL_HIGH>; 1687d514a74SPurna Chandra Mandal clocks = <&clock PB5CLK>; 1697d514a74SPurna Chandra Mandal status = "disabled"; 1707d514a74SPurna Chandra Mandal #address-cells = <1>; 1717d514a74SPurna Chandra Mandal #size-cells = <0>; 1727d514a74SPurna Chandra Mandal }; 173ac7eef71SPurna Chandra Mandal 174ac7eef71SPurna Chandra Mandal usb: musb@1f8e3000 { 175ac7eef71SPurna Chandra Mandal compatible = "microchip,pic32mzda-usb"; 176ac7eef71SPurna Chandra Mandal reg = <0x1f8e3000 0x1000>, 177ac7eef71SPurna Chandra Mandal <0x1f884000 0x1000>; 178ac7eef71SPurna Chandra Mandal reg-names = "mc", "control"; 179ac7eef71SPurna Chandra Mandal interrupts = <132 IRQ_TYPE_EDGE_RISING>, 180ac7eef71SPurna Chandra Mandal <133 IRQ_TYPE_LEVEL_HIGH>; 181ac7eef71SPurna Chandra Mandal clocks = <&clock PB5CLK>; 182ac7eef71SPurna Chandra Mandal clock-names = "usb_clk"; 183ac7eef71SPurna Chandra Mandal status = "disabled"; 184ac7eef71SPurna Chandra Mandal }; 185be961fa1SPurna Chandra Mandal}; 186