1f8c8ceddSGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2f8c8ceddSGregory CLEMENT/* 3f8c8ceddSGregory CLEMENT * Copyright (c) 2018 Microsemi Corporation 4f8c8ceddSGregory CLEMENT */ 5f8c8ceddSGregory CLEMENT 6f8c8ceddSGregory CLEMENT#include <dt-bindings/gpio/gpio.h> 7f8c8ceddSGregory CLEMENT 8f8c8ceddSGregory CLEMENT/ { 9f8c8ceddSGregory CLEMENT #address-cells = <1>; 10f8c8ceddSGregory CLEMENT #size-cells = <1>; 11f8c8ceddSGregory CLEMENT compatible = "mscc,luton"; 12f8c8ceddSGregory CLEMENT 13f8c8ceddSGregory CLEMENT cpus { 14f8c8ceddSGregory CLEMENT #address-cells = <1>; 15f8c8ceddSGregory CLEMENT #size-cells = <0>; 16f8c8ceddSGregory CLEMENT 17f8c8ceddSGregory CLEMENT cpu@0 { 18f8c8ceddSGregory CLEMENT compatible = "mips,mips24KEc"; 19f8c8ceddSGregory CLEMENT device_type = "cpu"; 20f8c8ceddSGregory CLEMENT reg = <0>; 21f8c8ceddSGregory CLEMENT }; 22f8c8ceddSGregory CLEMENT }; 23f8c8ceddSGregory CLEMENT 24f8c8ceddSGregory CLEMENT aliases { 25f8c8ceddSGregory CLEMENT serial0 = &uart0; 26f8c8ceddSGregory CLEMENT }; 27f8c8ceddSGregory CLEMENT 28*738f2b14SLars Povlsen sys_clk: sys-clk { 29*738f2b14SLars Povlsen compatible = "fixed-clock"; 30*738f2b14SLars Povlsen #clock-cells = <0>; 31*738f2b14SLars Povlsen clock-frequency = <250000000>; 32*738f2b14SLars Povlsen }; 33f8c8ceddSGregory CLEMENT ahb_clk: ahb-clk { 34f8c8ceddSGregory CLEMENT compatible = "fixed-clock"; 35f8c8ceddSGregory CLEMENT #clock-cells = <0>; 36f8c8ceddSGregory CLEMENT clock-frequency = <208333333>; 37f8c8ceddSGregory CLEMENT }; 38f8c8ceddSGregory CLEMENT 39f8c8ceddSGregory CLEMENT ahb { 40f8c8ceddSGregory CLEMENT compatible = "simple-bus"; 41f8c8ceddSGregory CLEMENT #address-cells = <1>; 42f8c8ceddSGregory CLEMENT #size-cells = <1>; 43f8c8ceddSGregory CLEMENT ranges = <0 0x60000000 0x10200000>; 44f8c8ceddSGregory CLEMENT 45f8c8ceddSGregory CLEMENT uart0: serial@10100000 { 46f8c8ceddSGregory CLEMENT pinctrl-0 = <&uart_pins>; 47f8c8ceddSGregory CLEMENT pinctrl-names = "default"; 48f8c8ceddSGregory CLEMENT 49f8c8ceddSGregory CLEMENT compatible = "ns16550a"; 50f8c8ceddSGregory CLEMENT reg = <0x10100000 0x20>; 51f8c8ceddSGregory CLEMENT clocks = <&ahb_clk>; 52f8c8ceddSGregory CLEMENT reg-io-width = <4>; 53f8c8ceddSGregory CLEMENT reg-shift = <2>; 54f8c8ceddSGregory CLEMENT 55f8c8ceddSGregory CLEMENT status = "disabled"; 56f8c8ceddSGregory CLEMENT }; 57f8c8ceddSGregory CLEMENT 58f8c8ceddSGregory CLEMENT gpio: pinctrl@70068 { 59f8c8ceddSGregory CLEMENT compatible = "mscc,luton-pinctrl"; 60f8c8ceddSGregory CLEMENT reg = <0x70068 0x68>; 61f8c8ceddSGregory CLEMENT gpio-controller; 62f8c8ceddSGregory CLEMENT #gpio-cells = <2>; 63f8c8ceddSGregory CLEMENT gpio-ranges = <&gpio 0 0 32>; 64f8c8ceddSGregory CLEMENT 65*738f2b14SLars Povlsen sgpio_pins: sgpio-pins { 66*738f2b14SLars Povlsen pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; 67*738f2b14SLars Povlsen function = "sio"; 68*738f2b14SLars Povlsen }; 69f8c8ceddSGregory CLEMENT uart_pins: uart-pins { 70f8c8ceddSGregory CLEMENT pins = "GPIO_30", "GPIO_31"; 71f8c8ceddSGregory CLEMENT function = "uart"; 72f8c8ceddSGregory CLEMENT }; 73*738f2b14SLars Povlsen }; 74f8c8ceddSGregory CLEMENT 75*738f2b14SLars Povlsen sgpio: gpio@70130 { 76*738f2b14SLars Povlsen compatible = "mscc,luton-sgpio"; 77*738f2b14SLars Povlsen status = "disabled"; 78*738f2b14SLars Povlsen clocks = <&sys_clk>; 79*738f2b14SLars Povlsen pinctrl-0 = <&sgpio_pins>; 80*738f2b14SLars Povlsen pinctrl-names = "default"; 81*738f2b14SLars Povlsen reg = <0x0070130 0x100>; 82*738f2b14SLars Povlsen gpio-controller; 83*738f2b14SLars Povlsen #gpio-cells = <2>; 84*738f2b14SLars Povlsen gpio-ranges = <&sgpio 0 0 64>; 85f8c8ceddSGregory CLEMENT }; 86f8c8ceddSGregory CLEMENT 87f8c8ceddSGregory CLEMENT gpio_spi_bitbang: gpio@10000064 { 88f8c8ceddSGregory CLEMENT compatible = "mscc,spi-bitbang-gpio"; 89f8c8ceddSGregory CLEMENT reg = <0x10000064 0x4>; 90f8c8ceddSGregory CLEMENT gpio-controller; 91f8c8ceddSGregory CLEMENT #gpio-cells = <2>; 92f8c8ceddSGregory CLEMENT 93f8c8ceddSGregory CLEMENT }; 94f8c8ceddSGregory CLEMENT 95f8c8ceddSGregory CLEMENT spi0: spi-bitbang { 96f8c8ceddSGregory CLEMENT compatible = "spi-gpio"; 97f8c8ceddSGregory CLEMENT status = "okay"; 98f8c8ceddSGregory CLEMENT gpio-sck = <&gpio_spi_bitbang 6 0>; 99f8c8ceddSGregory CLEMENT gpio-miso = <&gpio_spi_bitbang 0 0>; 100f8c8ceddSGregory CLEMENT gpio-mosi = <&gpio_spi_bitbang 5 0>; 101f8c8ceddSGregory CLEMENT cs-gpios = <&gpio_spi_bitbang 1 0>; 102f8c8ceddSGregory CLEMENT num-chipselects = <1>; 103f8c8ceddSGregory CLEMENT #address-cells = <1>; 104f8c8ceddSGregory CLEMENT #size-cells = <0>; 105f8c8ceddSGregory CLEMENT }; 106f8c8ceddSGregory CLEMENT }; 107f8c8ceddSGregory CLEMENT}; 108