1f8c8ceddSGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2f8c8ceddSGregory CLEMENT/* 3f8c8ceddSGregory CLEMENT * Copyright (c) 2018 Microsemi Corporation 4f8c8ceddSGregory CLEMENT */ 5f8c8ceddSGregory CLEMENT 6f8c8ceddSGregory CLEMENT/dts-v1/; 7f8c8ceddSGregory CLEMENT#include "mscc,luton.dtsi" 8f8c8ceddSGregory CLEMENT 9f8c8ceddSGregory CLEMENT/ { 10f8c8ceddSGregory CLEMENT model = "Luton10 PCB091 Reference Board"; 11f8c8ceddSGregory CLEMENT compatible = "mscc,luton-pcb091", "mscc,luton"; 12f8c8ceddSGregory CLEMENT 13f8c8ceddSGregory CLEMENT aliases { 14f8c8ceddSGregory CLEMENT serial0 = &uart0; 15f8c8ceddSGregory CLEMENT spi0 = &spi0; 16f8c8ceddSGregory CLEMENT }; 17f8c8ceddSGregory CLEMENT 18f8c8ceddSGregory CLEMENT chosen { 19f8c8ceddSGregory CLEMENT stdout-path = "serial0:115200n8"; 20f8c8ceddSGregory CLEMENT }; 21*738f2b14SLars Povlsen 22*738f2b14SLars Povlsen gpio-leds { 23*738f2b14SLars Povlsen compatible = "gpio-leds"; 24*738f2b14SLars Povlsen 25*738f2b14SLars Povlsen top_dimmer { 26*738f2b14SLars Povlsen label = "pcb091:top:dimmer"; 27*738f2b14SLars Povlsen gpios = <&gpio 29 GPIO_ACTIVE_LOW>; 28*738f2b14SLars Povlsen default-state = "on"; 29*738f2b14SLars Povlsen }; 30*738f2b14SLars Povlsen 31*738f2b14SLars Povlsen status_green { 32*738f2b14SLars Povlsen label = "pcb091:green:status"; 33*738f2b14SLars Povlsen gpios = <&sgpio 26 GPIO_ACTIVE_HIGH>; /* p26.0 */ 34*738f2b14SLars Povlsen default-state = "on"; 35*738f2b14SLars Povlsen }; 36*738f2b14SLars Povlsen 37*738f2b14SLars Povlsen status_red { 38*738f2b14SLars Povlsen label = "pcb091:red:status"; 39*738f2b14SLars Povlsen gpios = <&sgpio 58 GPIO_ACTIVE_HIGH>; /* p26.1 */ 40*738f2b14SLars Povlsen default-state = "off"; 41*738f2b14SLars Povlsen }; 42*738f2b14SLars Povlsen }; 43*738f2b14SLars Povlsen}; 44*738f2b14SLars Povlsen 45*738f2b14SLars Povlsen&sgpio { 46*738f2b14SLars Povlsen status = "okay"; 47*738f2b14SLars Povlsen mscc,sgpio-ports = <0xFFF000FF>; 48f8c8ceddSGregory CLEMENT}; 49f8c8ceddSGregory CLEMENT 50f8c8ceddSGregory CLEMENT&uart0 { 51f8c8ceddSGregory CLEMENT status = "okay"; 52f8c8ceddSGregory CLEMENT}; 53f8c8ceddSGregory CLEMENT 54f8c8ceddSGregory CLEMENT&spi0 { 55f8c8ceddSGregory CLEMENT status = "okay"; 56f8c8ceddSGregory CLEMENT spi-flash@0 { 57f8c8ceddSGregory CLEMENT compatible = "spi-flash"; 58f8c8ceddSGregory CLEMENT spi-max-frequency = <18000000>; /* input clock */ 59f8c8ceddSGregory CLEMENT reg = <0>; /* CS0 */ 60f8c8ceddSGregory CLEMENT spi-cs-high; 61f8c8ceddSGregory CLEMENT }; 62f8c8ceddSGregory CLEMENT}; 63f8c8ceddSGregory CLEMENT 64