1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 2b2b135d9SPaul Burton/* 3b2b135d9SPaul Burton * MIPS Coherence Manager (CM) Initialisation 4b2b135d9SPaul Burton * 5b2b135d9SPaul Burton * Copyright (c) 2016 Imagination Technologies Ltd. 6b2b135d9SPaul Burton */ 7b2b135d9SPaul Burton 8b2b135d9SPaul Burton#include <asm/addrspace.h> 9b2b135d9SPaul Burton#include <asm/asm.h> 10b2b135d9SPaul Burton#include <asm/cm.h> 11b2b135d9SPaul Burton#include <asm/mipsregs.h> 12b2b135d9SPaul Burton#include <asm/regdef.h> 13b2b135d9SPaul Burton 14b2b135d9SPaul BurtonLEAF(mips_cm_map) 15b2b135d9SPaul Burton /* Config3 must exist for a CM to be present */ 16b2b135d9SPaul Burton mfc0 t0, CP0_CONFIG, 1 17b2b135d9SPaul Burton bgez t0, 2f 18b2b135d9SPaul Burton mfc0 t0, CP0_CONFIG, 2 19b2b135d9SPaul Burton bgez t0, 2f 20b2b135d9SPaul Burton 21b2b135d9SPaul Burton /* Check Config3.CMGCR to determine CM presence */ 22b2b135d9SPaul Burton mfc0 t0, CP0_CONFIG, 3 23b2b135d9SPaul Burton and t0, t0, MIPS_CONF3_CMGCR 24b2b135d9SPaul Burton beqz t0, 2f 25b2b135d9SPaul Burton 26b2b135d9SPaul Burton /* Find the current physical GCR base address */ 27b2b135d9SPaul Burton1: MFC0 t0, CP0_CMGCRBASE 28b2b135d9SPaul Burton PTR_SLL t0, t0, 4 29b2b135d9SPaul Burton 30b2b135d9SPaul Burton /* If the GCRs are where we want, we're done */ 31b2b135d9SPaul Burton PTR_LI t1, CONFIG_MIPS_CM_BASE 32b2b135d9SPaul Burton beq t0, t1, 2f 33b2b135d9SPaul Burton 34b2b135d9SPaul Burton /* Move the GCRs to our configured base address */ 35b2b135d9SPaul Burton PTR_LI t2, CKSEG1 36b2b135d9SPaul Burton PTR_ADDU t0, t0, t2 37b2b135d9SPaul Burton sw zero, GCR_BASE_UPPER(t0) 38b2b135d9SPaul Burton sw t1, GCR_BASE(t0) 39b2b135d9SPaul Burton 40b2b135d9SPaul Burton /* Re-check the GCR base */ 41b2b135d9SPaul Burton b 1b 42b2b135d9SPaul Burton 43b2b135d9SPaul Burton2: jr ra 44b2b135d9SPaul Burton END(mips_cm_map) 45