xref: /openbmc/u-boot/arch/arm/mach-uniphier/dram/ddrphy-init.h (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
26dd34ae4SMasahiro Yamada /*
36dd34ae4SMasahiro Yamada  * Copyright (C) 2016 Socionext Inc.
46dd34ae4SMasahiro Yamada  */
56dd34ae4SMasahiro Yamada 
66dd34ae4SMasahiro Yamada #ifndef ARCH_DDRPHY_INIT_H
76dd34ae4SMasahiro Yamada #define ARCH_DDRPHY_INTT_H
86dd34ae4SMasahiro Yamada 
96dd34ae4SMasahiro Yamada #include <linux/compiler.h>
106dd34ae4SMasahiro Yamada #include <linux/types.h>
116dd34ae4SMasahiro Yamada 
126dd34ae4SMasahiro Yamada int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
136dd34ae4SMasahiro Yamada void ddrphy_prepare_training(void __iomem *phy_base, int rank);
146dd34ae4SMasahiro Yamada int ddrphy_training(void __iomem *phy_base);
156dd34ae4SMasahiro Yamada 
166dd34ae4SMasahiro Yamada #endif /* ARCH_DDRPHY_INT_H */
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