xref: /openbmc/u-boot/arch/arm/mach-tegra/tegra186/cache.S (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0 */
2b9ae6415SStephen Warren/*
3b9ae6415SStephen Warren * Copyright (c) 2016, NVIDIA CORPORATION.
4b9ae6415SStephen Warren */
5b9ae6415SStephen Warren
6b9ae6415SStephen Warren#include <config.h>
7b9ae6415SStephen Warren#include <linux/linkage.h>
8b9ae6415SStephen Warren
9b9ae6415SStephen Warren#define SMC_SIP_INVOKE_MCE		0x82FFFF00
10b9ae6415SStephen Warren#define MCE_SMC_ROC_FLUSH_CACHE		(SMC_SIP_INVOKE_MCE | 11)
11a8d05261SStephen Warren#define MCE_SMC_ROC_FLUSH_CACHE_ONLY	(SMC_SIP_INVOKE_MCE | 14)
12a8d05261SStephen Warren#define MCE_SMC_ROC_CLEAN_CACHE_ONLY	(SMC_SIP_INVOKE_MCE | 15)
13b9ae6415SStephen Warren
14a8d05261SStephen WarrenENTRY(__asm_tegra_cache_smc)
15b9ae6415SStephen Warren	mov	x1, #0
16b9ae6415SStephen Warren	mov	x2, #0
17b9ae6415SStephen Warren	mov	x3, #0
18b9ae6415SStephen Warren	mov	x4, #0
19b9ae6415SStephen Warren	mov	x5, #0
20b9ae6415SStephen Warren	mov	x6, #0
21b9ae6415SStephen Warren	smc	#0
22b9ae6415SStephen Warren	mov	x0, #0
23b9ae6415SStephen Warren	ret
24a8d05261SStephen WarrenENDPROC(__asm_invalidate_l3_dcache)
25a8d05261SStephen Warren
26a8d05261SStephen WarrenENTRY(__asm_invalidate_l3_dcache)
27a8d05261SStephen Warren	mov	x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff)
28a8d05261SStephen Warren	movk	x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16
29a8d05261SStephen Warren	b	__asm_tegra_cache_smc
30a8d05261SStephen WarrenENDPROC(__asm_invalidate_l3_dcache)
31a8d05261SStephen Warren
32a8d05261SStephen WarrenENTRY(__asm_flush_l3_dcache)
33a8d05261SStephen Warren	mov	x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff)
34a8d05261SStephen Warren	movk	x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16
35a8d05261SStephen Warren	b	__asm_tegra_cache_smc
361ab557a0SStephen WarrenENDPROC(__asm_flush_l3_dcache)
37a8d05261SStephen Warren
38a8d05261SStephen WarrenENTRY(__asm_invalidate_l3_icache)
39a8d05261SStephen Warren	mov	x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
40a8d05261SStephen Warren	movk	x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
41a8d05261SStephen Warren	b	__asm_tegra_cache_smc
42a8d05261SStephen WarrenENDPROC(__asm_invalidate_l3_icache)
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