1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2237c3637SMasahiro Yamada /* 3237c3637SMasahiro Yamada * Copyright (c) 2011 The Chromium OS Authors. 4237c3637SMasahiro Yamada */ 5237c3637SMasahiro Yamada 6237c3637SMasahiro Yamada #include <common.h> 7237c3637SMasahiro Yamada #include "emc.h" 8237c3637SMasahiro Yamada #include <asm/io.h> 9237c3637SMasahiro Yamada #include <asm/arch/clock.h> 10237c3637SMasahiro Yamada #include <asm/arch/emc.h> 11237c3637SMasahiro Yamada #include <asm/arch/pmu.h> 12237c3637SMasahiro Yamada #include <asm/arch/tegra.h> 13237c3637SMasahiro Yamada #include <asm/arch-tegra/ap.h> 14237c3637SMasahiro Yamada #include <asm/arch-tegra/clk_rst.h> 15237c3637SMasahiro Yamada #include <asm/arch-tegra/sys_proto.h> 16237c3637SMasahiro Yamada 17237c3637SMasahiro Yamada DECLARE_GLOBAL_DATA_PTR; 18237c3637SMasahiro Yamada 19237c3637SMasahiro Yamada /* These rates are hard-coded for now, until fdt provides them */ 20237c3637SMasahiro Yamada #define EMC_SDRAM_RATE_T20 (333000 * 2 * 1000) 21237c3637SMasahiro Yamada #define EMC_SDRAM_RATE_T25 (380000 * 2 * 1000) 22237c3637SMasahiro Yamada board_emc_init(void)23237c3637SMasahiro Yamadaint board_emc_init(void) 24237c3637SMasahiro Yamada { 25237c3637SMasahiro Yamada unsigned rate; 26237c3637SMasahiro Yamada 27237c3637SMasahiro Yamada switch (tegra_get_chip_sku()) { 28237c3637SMasahiro Yamada default: 29237c3637SMasahiro Yamada case TEGRA_SOC_T20: 30237c3637SMasahiro Yamada rate = EMC_SDRAM_RATE_T20; 31237c3637SMasahiro Yamada break; 32237c3637SMasahiro Yamada case TEGRA_SOC_T25: 33237c3637SMasahiro Yamada rate = EMC_SDRAM_RATE_T25; 34237c3637SMasahiro Yamada break; 35237c3637SMasahiro Yamada } 36237c3637SMasahiro Yamada return tegra_set_emc(gd->fdt_blob, rate); 37237c3637SMasahiro Yamada } 38