1*09f455dcSMasahiro Yamada /* 2*09f455dcSMasahiro Yamada * (C) Copyright 2010-2014 3*09f455dcSMasahiro Yamada * NVIDIA Corporation <www.nvidia.com> 4*09f455dcSMasahiro Yamada * 5*09f455dcSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 6*09f455dcSMasahiro Yamada */ 7*09f455dcSMasahiro Yamada #include <asm/types.h> 8*09f455dcSMasahiro Yamada 9*09f455dcSMasahiro Yamada /* Stabilization delays, in usec */ 10*09f455dcSMasahiro Yamada #define PLL_STABILIZATION_DELAY (300) 11*09f455dcSMasahiro Yamada #define IO_STABILIZATION_DELAY (1000) 12*09f455dcSMasahiro Yamada 13*09f455dcSMasahiro Yamada #if defined(CONFIG_TEGRA20) 14*09f455dcSMasahiro Yamada #define NVBL_PLLP_KHZ 216000 15*09f455dcSMasahiro Yamada #define CSITE_KHZ 144000 16*09f455dcSMasahiro Yamada #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \ 17*09f455dcSMasahiro Yamada defined(CONFIG_TEGRA124) 18*09f455dcSMasahiro Yamada #define NVBL_PLLP_KHZ 408000 19*09f455dcSMasahiro Yamada #define CSITE_KHZ 204000 20*09f455dcSMasahiro Yamada #else 21*09f455dcSMasahiro Yamada #error "Unknown Tegra chip!" 22*09f455dcSMasahiro Yamada #endif 23*09f455dcSMasahiro Yamada 24*09f455dcSMasahiro Yamada #define PLLX_ENABLED (1 << 30) 25*09f455dcSMasahiro Yamada #define CCLK_BURST_POLICY 0x20008888 26*09f455dcSMasahiro Yamada #define SUPER_CCLK_DIVIDER 0x80000000 27*09f455dcSMasahiro Yamada 28*09f455dcSMasahiro Yamada /* Calculate clock fractional divider value from ref and target frequencies */ 29*09f455dcSMasahiro Yamada #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) 30*09f455dcSMasahiro Yamada 31*09f455dcSMasahiro Yamada /* Calculate clock frequency value from reference and clock divider value */ 32*09f455dcSMasahiro Yamada #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) 33*09f455dcSMasahiro Yamada 34*09f455dcSMasahiro Yamada /* AVP/CPU ID */ 35*09f455dcSMasahiro Yamada #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ 36*09f455dcSMasahiro Yamada #define PG_UP_TAG_0 0x0 37*09f455dcSMasahiro Yamada 38*09f455dcSMasahiro Yamada #define CORESIGHT_UNLOCK 0xC5ACCE55; 39*09f455dcSMasahiro Yamada 40*09f455dcSMasahiro Yamada #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) 41*09f455dcSMasahiro Yamada #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) 42*09f455dcSMasahiro Yamada #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) 43*09f455dcSMasahiro Yamada #define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0) 44*09f455dcSMasahiro Yamada #define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0) 45*09f455dcSMasahiro Yamada 46*09f455dcSMasahiro Yamada #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) 47*09f455dcSMasahiro Yamada #define FLOW_MODE_STOP 2 48*09f455dcSMasahiro Yamada #define HALT_COP_EVENT_JTAG (1 << 28) 49*09f455dcSMasahiro Yamada #define HALT_COP_EVENT_IRQ_1 (1 << 11) 50*09f455dcSMasahiro Yamada #define HALT_COP_EVENT_FIQ_1 (1 << 9) 51*09f455dcSMasahiro Yamada 52*09f455dcSMasahiro Yamada #define FLOW_MODE_NONE 0 53*09f455dcSMasahiro Yamada 54*09f455dcSMasahiro Yamada #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) 55*09f455dcSMasahiro Yamada 56*09f455dcSMasahiro Yamada struct clk_pll_table { 57*09f455dcSMasahiro Yamada u16 n; 58*09f455dcSMasahiro Yamada u16 m; 59*09f455dcSMasahiro Yamada u8 p; 60*09f455dcSMasahiro Yamada u8 cpcon; 61*09f455dcSMasahiro Yamada }; 62*09f455dcSMasahiro Yamada 63*09f455dcSMasahiro Yamada void clock_enable_coresight(int enable); 64*09f455dcSMasahiro Yamada void enable_cpu_clock(int enable); 65*09f455dcSMasahiro Yamada void halt_avp(void) __attribute__ ((noreturn)); 66*09f455dcSMasahiro Yamada void init_pllx(void); 67*09f455dcSMasahiro Yamada void powerup_cpu(void); 68*09f455dcSMasahiro Yamada void reset_A9_cpu(int reset); 69*09f455dcSMasahiro Yamada void start_cpu(u32 reset_vector); 70*09f455dcSMasahiro Yamada int tegra_get_chip(void); 71*09f455dcSMasahiro Yamada int tegra_get_sku_info(void); 72*09f455dcSMasahiro Yamada int tegra_get_chip_sku(void); 73*09f455dcSMasahiro Yamada void adjust_pllp_out_freqs(void); 74*09f455dcSMasahiro Yamada void pmic_enable_cpu_vdd(void); 75