1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 */ 5 6 #ifndef _MACH_STM32_H_ 7 #define _MACH_STM32_H_ 8 9 /* 10 * Peripheral memory map 11 * only address used before device tree parsing 12 */ 13 #define STM32_RCC_BASE 0x50000000 14 #define STM32_PWR_BASE 0x50001000 15 #define STM32_DBGMCU_BASE 0x50081000 16 #define STM32_TZC_BASE 0x5C006000 17 #define STM32_ETZPC_BASE 0x5C007000 18 #define STM32_TAMP_BASE 0x5C00A000 19 20 #ifdef CONFIG_DEBUG_UART_BASE 21 /* hardcoded value can be only used for DEBUG UART */ 22 #define STM32_USART1_BASE 0x5C000000 23 #define STM32_USART2_BASE 0x4000E000 24 #define STM32_USART3_BASE 0x4000F000 25 #define STM32_UART4_BASE 0x40010000 26 #define STM32_UART5_BASE 0x40011000 27 #define STM32_USART6_BASE 0x44003000 28 #define STM32_UART7_BASE 0x40018000 29 #define STM32_UART8_BASE 0x40019000 30 #endif 31 32 #define STM32_SYSRAM_BASE 0x2FFC0000 33 #define STM32_SYSRAM_SIZE SZ_256K 34 35 #define STM32_DDR_BASE 0xC0000000 36 #define STM32_DDR_SIZE SZ_1G 37 38 #ifndef __ASSEMBLY__ 39 /* enumerated used to identify the SYSCON driver instance */ 40 enum { 41 STM32MP_SYSCON_UNKNOWN, 42 STM32MP_SYSCON_STGEN, 43 STM32MP_SYSCON_PWR, 44 }; 45 46 /* 47 * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT 48 * - boot device = bit 8:4 49 * - boot instance = bit 3:0 50 */ 51 #define BOOT_TYPE_MASK 0xF0 52 #define BOOT_TYPE_SHIFT 4 53 #define BOOT_INSTANCE_MASK 0x0F 54 #define BOOT_INSTANCE_SHIFT 0 55 56 enum boot_device { 57 BOOT_FLASH_SD = 0x10, 58 BOOT_FLASH_SD_1 = 0x11, 59 BOOT_FLASH_SD_2 = 0x12, 60 BOOT_FLASH_SD_3 = 0x13, 61 62 BOOT_FLASH_EMMC = 0x20, 63 BOOT_FLASH_EMMC_1 = 0x21, 64 BOOT_FLASH_EMMC_2 = 0x22, 65 BOOT_FLASH_EMMC_3 = 0x23, 66 67 BOOT_FLASH_NAND = 0x30, 68 BOOT_FLASH_NAND_FMC = 0x31, 69 70 BOOT_FLASH_NOR = 0x40, 71 BOOT_FLASH_NOR_QSPI = 0x41, 72 73 BOOT_SERIAL_UART = 0x50, 74 BOOT_SERIAL_UART_1 = 0x51, 75 BOOT_SERIAL_UART_2 = 0x52, 76 BOOT_SERIAL_UART_3 = 0x53, 77 BOOT_SERIAL_UART_4 = 0x54, 78 BOOT_SERIAL_UART_5 = 0x55, 79 BOOT_SERIAL_UART_6 = 0x56, 80 BOOT_SERIAL_UART_7 = 0x57, 81 BOOT_SERIAL_UART_8 = 0x58, 82 83 BOOT_SERIAL_USB = 0x60, 84 BOOT_SERIAL_USB_OTG = 0x62, 85 }; 86 87 /* TAMP registers */ 88 #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) 89 #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) 90 #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) 91 #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) 92 93 #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) 94 #define TAMP_BOOT_MODE_SHIFT 8 95 #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) 96 #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) 97 98 #endif /* __ASSEMBLY__*/ 99 #endif /* _MACH_STM32_H_ */ 100