1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 */ 5 #include <common.h> 6 #include <clk.h> 7 #include <debug_uart.h> 8 #include <asm/io.h> 9 #include <asm/arch/stm32.h> 10 #include <asm/arch/sys_proto.h> 11 #include <dm/uclass.h> 12 13 /* RCC register */ 14 #define RCC_TZCR (STM32_RCC_BASE + 0x00) 15 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) 16 #define RCC_BDCR (STM32_RCC_BASE + 0x0140) 17 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) 18 #define RCC_BDCR_VSWRST BIT(31) 19 #define RCC_BDCR_RTCSRC GENMASK(17, 16) 20 #define RCC_DBGCFGR_DBGCKEN BIT(8) 21 22 /* Security register */ 23 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) 24 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) 25 26 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) 27 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) 28 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) 29 30 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) 31 32 #define PWR_CR1 (STM32_PWR_BASE + 0x00) 33 #define PWR_CR1_DBP BIT(8) 34 35 /* DBGMCU register */ 36 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) 37 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) 38 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) 39 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) 40 #define DBGMCU_IDC_DEV_ID_SHIFT 0 41 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) 42 #define DBGMCU_IDC_REV_ID_SHIFT 16 43 44 /* boot interface from Bootrom 45 * - boot instance = bit 31:16 46 * - boot device = bit 15:0 47 */ 48 #define BOOTROM_PARAM_ADDR 0x2FFC0078 49 #define BOOTROM_MODE_MASK GENMASK(15, 0) 50 #define BOOTROM_MODE_SHIFT 0 51 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16) 52 #define BOOTROM_INSTANCE_SHIFT 16 53 54 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 55 static void security_init(void) 56 { 57 /* Disable the backup domain write protection */ 58 /* the protection is enable at each reset by hardware */ 59 /* And must be disable by software */ 60 setbits_le32(PWR_CR1, PWR_CR1_DBP); 61 62 while (!(readl(PWR_CR1) & PWR_CR1_DBP)) 63 ; 64 65 /* If RTC clock isn't enable so this is a cold boot then we need 66 * to reset the backup domain 67 */ 68 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { 69 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); 70 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) 71 ; 72 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); 73 } 74 75 /* allow non secure access in Write/Read for all peripheral */ 76 writel(GENMASK(25, 0), ETZPC_DECPROT0); 77 78 /* Open SYSRAM for no secure access */ 79 writel(0x0, ETZPC_TZMA1_SIZE); 80 81 /* enable TZC1 TZC2 clock */ 82 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); 83 84 /* Region 0 set to no access by default */ 85 /* bit 0 / 16 => nsaid0 read/write Enable 86 * bit 1 / 17 => nsaid1 read/write Enable 87 * ... 88 * bit 15 / 31 => nsaid15 read/write Enable 89 */ 90 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); 91 /* bit 30 / 31 => Secure Global Enable : write/read */ 92 /* bit 0 / 1 => Region Enable for filter 0/1 */ 93 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); 94 95 /* Enable Filter 0 and 1 */ 96 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); 97 98 /* RCC trust zone deactivated */ 99 writel(0x0, RCC_TZCR); 100 101 /* TAMP: deactivate the internal tamper 102 * Bit 23 ITAMP8E: monotonic counter overflow 103 * Bit 20 ITAMP5E: RTC calendar overflow 104 * Bit 19 ITAMP4E: HSE monitoring 105 * Bit 18 ITAMP3E: LSE monitoring 106 * Bit 16 ITAMP1E: RTC power domain supply monitoring 107 */ 108 writel(0x0, TAMP_CR1); 109 } 110 111 /* 112 * Debug init 113 */ 114 static void dbgmcu_init(void) 115 { 116 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); 117 118 /* Freeze IWDG2 if Cortex-A7 is in debug mode */ 119 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); 120 } 121 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ 122 123 static u32 get_bootmode(void) 124 { 125 u32 boot_mode; 126 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 127 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); 128 u32 bootrom_device, bootrom_instance; 129 130 bootrom_device = 131 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; 132 bootrom_instance = 133 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; 134 boot_mode = 135 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | 136 ((bootrom_instance << BOOT_INSTANCE_SHIFT) & 137 BOOT_INSTANCE_MASK); 138 139 /* save the boot mode in TAMP backup register */ 140 clrsetbits_le32(TAMP_BOOT_CONTEXT, 141 TAMP_BOOT_MODE_MASK, 142 boot_mode << TAMP_BOOT_MODE_SHIFT); 143 #else 144 /* read TAMP backup register */ 145 boot_mode = (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> 146 TAMP_BOOT_MODE_SHIFT; 147 #endif 148 return boot_mode; 149 } 150 151 /* 152 * Early system init 153 */ 154 int arch_cpu_init(void) 155 { 156 u32 boot_mode; 157 158 /* early armv7 timer init: needed for polling */ 159 timer_init(); 160 161 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 162 dbgmcu_init(); 163 164 security_init(); 165 #endif 166 167 /* get bootmode from BootRom context: saved in TAMP register */ 168 boot_mode = get_bootmode(); 169 170 if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) 171 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; 172 #if defined(CONFIG_DEBUG_UART) && \ 173 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 174 else 175 debug_uart_init(); 176 #endif 177 178 return 0; 179 } 180 181 void enable_caches(void) 182 { 183 /* Enable D-cache. I-cache is already enabled in start.S */ 184 dcache_enable(); 185 } 186 187 static u32 read_idc(void) 188 { 189 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); 190 191 return readl(DBGMCU_IDC); 192 } 193 194 u32 get_cpu_rev(void) 195 { 196 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; 197 } 198 199 u32 get_cpu_type(void) 200 { 201 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; 202 } 203 204 #if defined(CONFIG_DISPLAY_CPUINFO) 205 int print_cpuinfo(void) 206 { 207 char *cpu_s, *cpu_r; 208 209 switch (get_cpu_type()) { 210 case CPU_STMP32MP15x: 211 cpu_s = "15x"; 212 break; 213 default: 214 cpu_s = "?"; 215 break; 216 } 217 218 switch (get_cpu_rev()) { 219 case CPU_REVA: 220 cpu_r = "A"; 221 break; 222 case CPU_REVB: 223 cpu_r = "B"; 224 break; 225 default: 226 cpu_r = "?"; 227 break; 228 } 229 230 printf("CPU: STM32MP%s.%s\n", cpu_s, cpu_r); 231 232 return 0; 233 } 234 #endif /* CONFIG_DISPLAY_CPUINFO */ 235 236 static void setup_boot_mode(void) 237 { 238 char cmd[60]; 239 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); 240 u32 boot_mode = 241 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; 242 int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; 243 244 pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d\n", 245 __func__, boot_ctx, boot_mode, instance); 246 247 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { 248 case BOOT_SERIAL_UART: 249 sprintf(cmd, "%d", instance); 250 env_set("boot_device", "uart"); 251 env_set("boot_instance", cmd); 252 break; 253 case BOOT_SERIAL_USB: 254 env_set("boot_device", "usb"); 255 env_set("boot_instance", "0"); 256 break; 257 case BOOT_FLASH_SD: 258 case BOOT_FLASH_EMMC: 259 sprintf(cmd, "%d", instance); 260 env_set("boot_device", "mmc"); 261 env_set("boot_instance", cmd); 262 break; 263 case BOOT_FLASH_NAND: 264 env_set("boot_device", "nand"); 265 env_set("boot_instance", "0"); 266 break; 267 case BOOT_FLASH_NOR: 268 env_set("boot_device", "nor"); 269 env_set("boot_instance", "0"); 270 break; 271 default: 272 pr_debug("unexpected boot mode = %x\n", boot_mode); 273 break; 274 } 275 } 276 277 int arch_misc_init(void) 278 { 279 setup_boot_mode(); 280 281 return 0; 282 } 283