1 /* 2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <asm/io.h> 9 #include <asm/arch/stm32.h> 10 #include <asm/arch/sys_proto.h> 11 12 /* RCC register */ 13 #define RCC_TZCR (STM32_RCC_BASE + 0x00) 14 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) 15 #define RCC_BDCR (STM32_RCC_BASE + 0x0140) 16 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) 17 #define RCC_BDCR_VSWRST BIT(31) 18 #define RCC_BDCR_RTCSRC GENMASK(17, 16) 19 #define RCC_DBGCFGR_DBGCKEN BIT(8) 20 21 /* Security register */ 22 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) 23 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) 24 25 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) 26 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) 27 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) 28 29 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) 30 31 #define PWR_CR1 (STM32_PWR_BASE + 0x00) 32 #define PWR_CR1_DBP BIT(8) 33 34 /* DBGMCU register */ 35 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) 36 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) 37 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) 38 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) 39 #define DBGMCU_IDC_DEV_ID_SHIFT 0 40 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) 41 #define DBGMCU_IDC_REV_ID_SHIFT 16 42 43 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 44 static void security_init(void) 45 { 46 /* Disable the backup domain write protection */ 47 /* the protection is enable at each reset by hardware */ 48 /* And must be disable by software */ 49 setbits_le32(PWR_CR1, PWR_CR1_DBP); 50 51 while (!(readl(PWR_CR1) & PWR_CR1_DBP)) 52 ; 53 54 /* If RTC clock isn't enable so this is a cold boot then we need 55 * to reset the backup domain 56 */ 57 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { 58 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); 59 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) 60 ; 61 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); 62 } 63 64 /* allow non secure access in Write/Read for all peripheral */ 65 writel(GENMASK(25, 0), ETZPC_DECPROT0); 66 67 /* Open SYSRAM for no secure access */ 68 writel(0x0, ETZPC_TZMA1_SIZE); 69 70 /* enable TZC1 TZC2 clock */ 71 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); 72 73 /* Region 0 set to no access by default */ 74 /* bit 0 / 16 => nsaid0 read/write Enable 75 * bit 1 / 17 => nsaid1 read/write Enable 76 * ... 77 * bit 15 / 31 => nsaid15 read/write Enable 78 */ 79 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); 80 /* bit 30 / 31 => Secure Global Enable : write/read */ 81 /* bit 0 / 1 => Region Enable for filter 0/1 */ 82 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); 83 84 /* Enable Filter 0 and 1 */ 85 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); 86 87 /* RCC trust zone deactivated */ 88 writel(0x0, RCC_TZCR); 89 90 /* TAMP: deactivate the internal tamper 91 * Bit 23 ITAMP8E: monotonic counter overflow 92 * Bit 20 ITAMP5E: RTC calendar overflow 93 * Bit 19 ITAMP4E: HSE monitoring 94 * Bit 18 ITAMP3E: LSE monitoring 95 * Bit 16 ITAMP1E: RTC power domain supply monitoring 96 */ 97 writel(0x0, TAMP_CR1); 98 } 99 100 /* 101 * Debug init 102 */ 103 static void dbgmcu_init(void) 104 { 105 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); 106 107 /* Freeze IWDG2 if Cortex-A7 is in debug mode */ 108 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); 109 } 110 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ 111 112 int arch_cpu_init(void) 113 { 114 /* early armv7 timer init: needed for polling */ 115 timer_init(); 116 117 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 118 dbgmcu_init(); 119 120 security_init(); 121 #endif 122 123 return 0; 124 } 125 126 void enable_caches(void) 127 { 128 /* Enable D-cache. I-cache is already enabled in start.S */ 129 dcache_enable(); 130 } 131 132 static u32 read_idc(void) 133 { 134 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); 135 136 return readl(DBGMCU_IDC); 137 } 138 139 u32 get_cpu_rev(void) 140 { 141 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; 142 } 143 144 u32 get_cpu_type(void) 145 { 146 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; 147 } 148 149 #if defined(CONFIG_DISPLAY_CPUINFO) 150 int print_cpuinfo(void) 151 { 152 char *cpu_s, *cpu_r; 153 154 switch (get_cpu_type()) { 155 case CPU_STMP32MP15x: 156 cpu_s = "15x"; 157 break; 158 default: 159 cpu_s = "?"; 160 break; 161 } 162 163 switch (get_cpu_rev()) { 164 case CPU_REVA: 165 cpu_r = "A"; 166 break; 167 case CPU_REVB: 168 cpu_r = "B"; 169 break; 170 default: 171 cpu_r = "?"; 172 break; 173 } 174 175 printf("CPU: STM32MP%s.%s\n", cpu_s, cpu_r); 176 177 return 0; 178 } 179 #endif /* CONFIG_DISPLAY_CPUINFO */ 180 181 void reset_cpu(ulong addr) 182 { 183 } 184