1*83d290c5STom Rini /* SPDX-License-Identifier: BSD-3-Clause */ 26867e19aSTien Fong Chee /* 36867e19aSTien Fong Chee * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 46867e19aSTien Fong Chee * All rights reserved. 56867e19aSTien Fong Chee */ 66867e19aSTien Fong Chee 76867e19aSTien Fong Chee #ifndef _FPGA_MANAGER_GEN5_H_ 86867e19aSTien Fong Chee #define _FPGA_MANAGER_GEN5_H_ 96867e19aSTien Fong Chee 106867e19aSTien Fong Chee #define FPGAMGRREGS_STAT_MODE_MASK 0x7 116867e19aSTien Fong Chee #define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 126867e19aSTien Fong Chee #define FPGAMGRREGS_STAT_MSEL_LSB 3 136867e19aSTien Fong Chee 146867e19aSTien Fong Chee #define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9) 156867e19aSTien Fong Chee #define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8) 166867e19aSTien Fong Chee #define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2) 176867e19aSTien Fong Chee #define FPGAMGRREGS_CTRL_NCE_MASK BIT(1) 186867e19aSTien Fong Chee #define FPGAMGRREGS_CTRL_EN_MASK BIT(0) 196867e19aSTien Fong Chee #define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 206867e19aSTien Fong Chee 216867e19aSTien Fong Chee #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3) 226867e19aSTien Fong Chee #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2) 236867e19aSTien Fong Chee #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1) 246867e19aSTien Fong Chee #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0) 256867e19aSTien Fong Chee 266867e19aSTien Fong Chee /* FPGA Mode */ 276867e19aSTien Fong Chee #define FPGAMGRREGS_MODE_FPGAOFF 0x0 286867e19aSTien Fong Chee #define FPGAMGRREGS_MODE_RESETPHASE 0x1 296867e19aSTien Fong Chee #define FPGAMGRREGS_MODE_CFGPHASE 0x2 306867e19aSTien Fong Chee #define FPGAMGRREGS_MODE_INITPHASE 0x3 316867e19aSTien Fong Chee #define FPGAMGRREGS_MODE_USERMODE 0x4 326867e19aSTien Fong Chee #define FPGAMGRREGS_MODE_UNKNOWN 0x5 336867e19aSTien Fong Chee 346867e19aSTien Fong Chee #ifndef __ASSEMBLY__ 356867e19aSTien Fong Chee 366867e19aSTien Fong Chee struct socfpga_fpga_manager { 376867e19aSTien Fong Chee /* FPGA Manager Module */ 386867e19aSTien Fong Chee u32 stat; /* 0x00 */ 396867e19aSTien Fong Chee u32 ctrl; 406867e19aSTien Fong Chee u32 dclkcnt; 416867e19aSTien Fong Chee u32 dclkstat; 426867e19aSTien Fong Chee u32 gpo; /* 0x10 */ 436867e19aSTien Fong Chee u32 gpi; 446867e19aSTien Fong Chee u32 misci; /* 0x18 */ 456867e19aSTien Fong Chee u32 _pad_0x1c_0x82c[517]; 466867e19aSTien Fong Chee 476867e19aSTien Fong Chee /* Configuration Monitor (MON) Registers */ 486867e19aSTien Fong Chee u32 gpio_inten; /* 0x830 */ 496867e19aSTien Fong Chee u32 gpio_intmask; 506867e19aSTien Fong Chee u32 gpio_inttype_level; 516867e19aSTien Fong Chee u32 gpio_int_polarity; 526867e19aSTien Fong Chee u32 gpio_intstatus; /* 0x840 */ 536867e19aSTien Fong Chee u32 gpio_raw_intstatus; 546867e19aSTien Fong Chee u32 _pad_0x848; 556867e19aSTien Fong Chee u32 gpio_porta_eoi; 566867e19aSTien Fong Chee u32 gpio_ext_porta; /* 0x850 */ 576867e19aSTien Fong Chee u32 _pad_0x854_0x85c[3]; 586867e19aSTien Fong Chee u32 gpio_1s_sync; /* 0x860 */ 596867e19aSTien Fong Chee u32 _pad_0x864_0x868[2]; 606867e19aSTien Fong Chee u32 gpio_ver_id_code; 616867e19aSTien Fong Chee u32 gpio_config_reg2; /* 0x870 */ 626867e19aSTien Fong Chee u32 gpio_config_reg1; 636867e19aSTien Fong Chee }; 646867e19aSTien Fong Chee 656867e19aSTien Fong Chee #endif /* __ASSEMBLY__ */ 666867e19aSTien Fong Chee 676867e19aSTien Fong Chee #endif /* _FPGA_MANAGER_GEN5_H_ */ 68