1*83d290c5STom Rini /* SPDX-License-Identifier: BSD-3-Clause */ 230088b09SMasahiro Yamada /* 36867e19aSTien Fong Chee * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 430088b09SMasahiro Yamada * All rights reserved. 530088b09SMasahiro Yamada */ 630088b09SMasahiro Yamada 730088b09SMasahiro Yamada #ifndef _FPGA_MANAGER_H_ 830088b09SMasahiro Yamada #define _FPGA_MANAGER_H_ 930088b09SMasahiro Yamada 1030088b09SMasahiro Yamada #include <altera.h> 1130088b09SMasahiro Yamada 126867e19aSTien Fong Chee #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 136867e19aSTien Fong Chee #include <asm/arch/fpga_manager_gen5.h> 142baa9972STien Fong Chee #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 152baa9972STien Fong Chee #include <asm/arch/fpga_manager_arria10.h> 166867e19aSTien Fong Chee #endif 1730088b09SMasahiro Yamada 1830088b09SMasahiro Yamada /* FPGA CD Ratio Value */ 1930088b09SMasahiro Yamada #define CDRATIO_x1 0x0 2030088b09SMasahiro Yamada #define CDRATIO_x2 0x1 2130088b09SMasahiro Yamada #define CDRATIO_x4 0x2 2230088b09SMasahiro Yamada #define CDRATIO_x8 0x3 2330088b09SMasahiro Yamada 246867e19aSTien Fong Chee #ifndef __ASSEMBLY__ 2530088b09SMasahiro Yamada 266867e19aSTien Fong Chee /* Common prototypes */ 276867e19aSTien Fong Chee int fpgamgr_get_mode(void); 286867e19aSTien Fong Chee int fpgamgr_poll_fpga_ready(void); 296867e19aSTien Fong Chee void fpgamgr_program_write(const void *rbf_data, size_t rbf_size); 306867e19aSTien Fong Chee int fpgamgr_test_fpga_ready(void); 316867e19aSTien Fong Chee int fpgamgr_dclkcnt_set(unsigned long cnt); 326867e19aSTien Fong Chee 336867e19aSTien Fong Chee #endif /* __ASSEMBLY__ */ 3430088b09SMasahiro Yamada #endif /* _FPGA_MANAGER_H_ */ 35