1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 25a7152e4SDinh Nguyen /* 3d83b8193SLey Foon Tan * Copyright (C) 2014-2017 Altera Corporation <www.altera.com> 45a7152e4SDinh Nguyen */ 55a7152e4SDinh Nguyen 65a7152e4SDinh Nguyen #ifndef _SOCFPGA_A10_BASE_HARDWARE_H_ 75a7152e4SDinh Nguyen #define _SOCFPGA_A10_BASE_HARDWARE_H_ 85a7152e4SDinh Nguyen 95a7152e4SDinh Nguyen #define SOCFPGA_EMAC0_ADDRESS 0xff800000 105a7152e4SDinh Nguyen #define SOCFPGA_EMAC1_ADDRESS 0xff802000 115a7152e4SDinh Nguyen #define SOCFPGA_EMAC2_ADDRESS 0xff804000 125a7152e4SDinh Nguyen #define SOCFPGA_SDMMC_ADDRESS 0xff808000 135a7152e4SDinh Nguyen #define SOCFPGA_QSPIREGS_ADDRESS 0xff809000 145a7152e4SDinh Nguyen #define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 155a7152e4SDinh Nguyen #define SOCFPGA_UART1_ADDRESS 0xffc02100 165a7152e4SDinh Nguyen #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xffcfa000 175a7152e4SDinh Nguyen #define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400 185a7152e4SDinh Nguyen #define SOCFPGA_FPGAMGRREGS_ADDRESS 0xffd03000 195a7152e4SDinh Nguyen #define SOCFPGA_L4WD0_ADDRESS 0xffd00200 205a7152e4SDinh Nguyen #define SOCFPGA_SYSMGR_ADDRESS 0xffd06000 215a7152e4SDinh Nguyen #define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS 0xffd07000 225a7152e4SDinh Nguyen #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd07200 235a7152e4SDinh Nguyen #define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS 0xffd07300 245a7152e4SDinh Nguyen #define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS 0xffd07400 255a7152e4SDinh Nguyen #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 265a7152e4SDinh Nguyen #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 275a7152e4SDinh Nguyen #define SOCFPGA_MPUSCU_ADDRESS 0xffffc000 285a7152e4SDinh Nguyen #define SOCFPGA_MPUL2_ADDRESS 0xfffff000 295a7152e4SDinh Nguyen #define SOCFPGA_I2C0_ADDRESS 0xffc02200 305a7152e4SDinh Nguyen #define SOCFPGA_I2C1_ADDRESS 0xffc02300 31d83b8193SLey Foon Tan #define SOCFPGA_I2C2_ADDRESS 0xffc02400 32d83b8193SLey Foon Tan #define SOCFPGA_I2C3_ADDRESS 0xffc02500 33d83b8193SLey Foon Tan #define SOCFPGA_I2C4_ADDRESS 0xffc02600 345a7152e4SDinh Nguyen 355a7152e4SDinh Nguyen #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 365a7152e4SDinh Nguyen #define SOCFPGA_UART0_ADDRESS 0xffc02000 375a7152e4SDinh Nguyen #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 38d83b8193SLey Foon Tan #define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100 395a7152e4SDinh Nguyen #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 405a7152e4SDinh Nguyen #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 415a7152e4SDinh Nguyen 425a7152e4SDinh Nguyen #define SOCFPGA_SDR_ADDRESS 0xffcfb000 43d83b8193SLey Foon Tan #define SOCFPGA_NOC_L4_PRIV_FLT_OFST 0xffd11000 445a7152e4SDinh Nguyen #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400 455a7152e4SDinh Nguyen #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200 465a7152e4SDinh Nguyen #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300 475a7152e4SDinh Nguyen #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400 48d83b8193SLey Foon Tan #define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500 495a7152e4SDinh Nguyen 505a7152e4SDinh Nguyen #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */ 51